Apple’s A14 Packs 134M Transistors/mm²

https://semianalysis.com/apples-a14-packs-134-million-transistors-mm2-but-falls-far-short-of-tsmcs-density-claims/

by jonbaer • 6 years ago

314 175 6 years ago

pwinnski• 6 years ago

"A14 comes in at a cool 78% effective transistor density when compared to theoretical density." Wowsers. Apparently SRAM is the limiting factor.

jhloa2• 6 years ago

If SRAM is as ubiquitous throughout chip designs as the article suggests, wouldn't that mean the theoretical density prediction is off?

Symmetry3• 6 years ago

Time for eDRAM! Ok, this process doesn't support eDRAM. Also, I don't understand the SRAM scaling failure here and I don't know if it would apply to eDRAM too. But it's something to think about given the increasing importance of wire delay.

callesgg• 6 years ago

The theoretical maximum density is probably based on some type of physical law or just a simplified model. That is often what people talk about when they talk about theoretical maximums/minimums.

Like if you have a box of dimensions 10x10x10cm the theoretical maximum number of dice of dimension 1x1x1cm you can fit in the box is 1000 dices. Chances are you won’t get 1000 dices in to the box as the world is more complex than the theoretical model we used for the scenario.

rdw• 6 years ago

The article says that Apple isn't making full use of the 5nm process node, and blames lack of SRAM scaling for it (presumably due to the large amount of L3 cache). Is this a problem that all processors are about to hit, or is this going to be overcome once process engineers are more familiar with 5nm?

FullyFunctional4• 6 years ago

They optimize SRAM far in advance of introducing the process, after all this is one of the most critical components. It's very unlikely you'll see any further SRAM improvement on this process, but a process optimization can improve it (and everything else).

ajross• 6 years ago

This bit didn't make a lot of sense to me. SRAM is routinely the MOST optimized and MOST worried-over aspect of silicon layout. SRAM cell architectures get hand-optimized carefully years in advance of any process improvements. They aren't just logic that gets spit out of generic tooling.

So while it would make sense that a new process would have new design rule that didn't map well to older EDA tooling, it's harder to see that argument holding for SRAM. If SRAM isn't scaling, why is general logic?

hajile• 6 years ago

It can be noted that the cell size reduction rate from 2017 to 2018 to 2019 is much slower than the rate for preceding years 2011 to 2017, showing that SRAM cells have not been scaling at the same rate as logic in general. At IEDM 2019, the 5nm process was quoted to have 1.84x logic density improvement compared to 1.35x SRAM density improvement[1]

0.021um per cell [1] for TSMC N5 vs 0.027um per cell [0] for TSMC N7.

Even if Apple did everything right, they'd still be behind due to the limits of the process.

[0]https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells...

[1]https://semiwiki.com/semiconductor-manufacturers/tsmc/283487...

urthor3• 6 years ago

It's not uncommon for different components to scale differently.

They're often literally made out of different metals that have different resistance characteristics at different wire gauges, for example.

Interconnects was a very famous case, but many aspects of electrical engineering change when you get that small, because hey if you shrink the diameter of a wire by half guess what happens to the volume.

Semiconductor engineering is the field of dealing with a thousand of these tiny problems, and an improvement in the photolithography wavelengths is actually an abstraction of solving the thousands of tiny problems involved with all the different materials.

talentedcoin• 6 years ago

I think this is cool if they’re the future of the Mac, but aren’t these chips just wasted in the iPad? I say this as an iPad Pro (1st-gen) owner ... it’s already way more processing power than I can really use, because after trying for months to get a sensible workflow going (mostly based around Pythonista, Editorial and RealVNC) I’ve relegated it to a OneNote and Netflix machine. What’s the point other than the coolness factor? Is it some future AR-type application?

Moto7451• 6 years ago

My understanding from talking to friends who work at Apple and some of the product briefs is a lot of the hardware is used for video and photo processing. Video games take advantage of the extra CPU/GPU power as well.

I don’t think that’s all that Apple specific as there are increased ISPs and security chips on other phones as well.

samatman3• 6 years ago

Not if you start juggling several streams of 4k video, it's not.

Also, one can play games on an iPad, and games will soak up arbitrary amounts of CPU and GPU power.

jagged-chisel• 6 years ago

I'm sure Apple consider the iPad Pro as a testing ground for these chips.

kitotik• 6 years ago

Audio and Video work will take all the transistors you can throw at it. Things like GarageBand and 3rd party software synthesizers can easily max out even latest gen iPad Pros. Not to mention games…

Cookingboy• 6 years ago

What’s the point other than the coolness factor?

So Genshin Impact can look and run beautifully XD

manmal• 6 years ago

Having a more-powerful-than-necessary CPU has many benefits, here are some:

- Less heat produced > allows for smaller heatsinks and, as a result, smaller devices or bigger components

- Performance bottlenecks become less likely

- Features like 120hz display refresh rate become possible without the user noticing degradation

- Faster OS boot and app starts

- Ability to do more work locally vs using a server (see the many ML features)

- Tech debt in system code is less of an issue - code can be shipped early and optimized later

bhj• 6 years ago

Battery life. The faster a task is completed (at a given power cost) the sooner the CPU can go back to standby.

Polylactic_acid• 6 years ago

Not to mention it extends the life of the device. If a device is only just good enough for now, what will it be like in 4 years time. I currently use a 6 year old ipad air 2 and it feels very snappy and does everything I use it for well. Apple also tends to stop updates when the hardware is no longer capable of running the next OS smoothly.

centimeter• 6 years ago

I bought my iPad Pro because it offered the smoothest RAW photo proofing process of any product I've used. A lot of this is obviously up to software as well as hardware, but still - the beefy processor is useful here.

mceachen• 6 years ago

Faster CPUs certainly help everything go faster, but what you're asking of the CPU may matter much more than how fast the CPU is.

RAW processing is actually a really interesting application, and rendering time depends heavily on what you do with the bits from the sensor.

If you use non-linear interpolation, 2-50x the time to build.

If you do highlight recovery, 2-5x the time to build.

If you only need half the native resolution, build time may be reduced 2-4x.

Basically "viewing a RAW image" can take 100 milliseconds or 15 seconds (on the same hardware!), depending on how you're interpreting the sensor data.

(Source: playing with dcraw and libraw to rasterize raw images for PhotoStructure)

urthor3• 6 years ago

Never underestimate the PUBG Mobile/Genshin Impact demographic basically.

There's a lot of corner cases there where certain consumers value it a lot.

Also performance per watt is a huge deal. The expanded power envelope that improved PPW brings allows 120hz displays which are battery hogs.

Reason077• 6 years ago

I wonder if Apple Silicon means we might finally get PUBG on Mac. If they can make it work on an iPad, they can make it work on a Mac with similar hardware... right?!

I'm already missing the glorious few months that PUBG could be played on Mac via Stadia.

jiggawatts3• 6 years ago

I was just looking into optimising a large web application.

I told the customer that using a caching layer such as a CDN would help paper over the worst of the inefficiencies in their application and the network stack.

That was true! The download times halved.

However, benchmarks with F12 developer tools showed that while downloads reduced from 200ms to 100ms, the overall load times were still seconds, of which about 50% was actual CPU time.

(This is typical of large, complex sites built by non-experts or organisations where performance is not a primary concern.)

Web sites like these perform very noticeably better if you have more CPU cores or faster CPU cores.

Essentially, CDNs are easy to deploy and 5G provides nearly gigabit download speeds, so the bottleneck has shifted back to the CPU for a lot of the web.

jacobolus• 6 years ago

There is no speed of computer which cannot be overwhelmed by badly written code.

I guess your point is that sloppy web developers / web companies make poorly performing code and shift the burden of handling it out to visitors’ machines, so those machines have to keep improving to not be left behind?

That might be true, but is pretty depressing.

Godel_unicode2• 6 years ago

Sounds like the argument here is "buy an iPad pro so frontend developers don't need to learn optimization"...?

threeseed• 6 years ago

Many professionals are using iPad Pro for audio e.g. DAW and video e.g. editing.

72deluxe• 6 years ago

What DAW are they using? I use my iPad as a remote for Presonus Studio One sometimes, but I couldn't consider using it as the recording system itself, since the AU and VST accessibility isn't there.

I would also use my iPad as a synthesiser (eg. Magellan) but then record the audio to a "real" computer, ie the Mac, via a recording interface.

wincy2• 6 years ago

I sold my 2080ti and am playing Eve Echoes (new, mobile version of EVE Online) and Among Us, and Civ VI on the 2nd gen iPad Pro I bought used with less than half of the proceeds. The battery lasts a good long time and it feels pretty good to be able to play these full sized games on a screen like this. When I'm not using it the toddler watches some kids shows, and with the keyboard case I can type almost as quickly as I can on my 15" Macbook pro. If it had XCode I'd be set, honestly.

saagarjha6• 6 years ago

I work on a x86 interpreter that is only usable because of Apple's massive investment into these chips over the last couple years. I doubt that is what Apple was designing them for, but they are very useful to have as an application developer.

djxfade• 6 years ago

Are you the developer of iSH by any chance? If so, very cool project. Was it hard to get it published in the App Store?

megablast• 6 years ago

That is the way you want it. You don’t want it the other way.

vmception• 6 years ago

Even if assuming they were wasted, lower the production cost for everyone else that is not wasting them

fomine3• 6 years ago

Apple's SoC works really great and impressive, but I don't know why I need such spec for Phone. Even A12 is still great for most workloads. Apple improves camera functionality by its performance but just camera? I wish they find useful uses other than cameras.

exabrial• 6 years ago

For comparison I was trying to nail down what Intel's 7nm process is, but I've found answers between 120nm and 215nm. If anyone knows, that'd be an interesting comparison.

kop316• 6 years ago

Considering this news:

https://finance.yahoo.com/news/intel-now-ordering-chips-tsmc...

I sincerely doubt Intel will ever disclose it.

wmf4• 6 years ago

Intel's prior CEO, Brian Krzanich, mentioned that 7-nanometer will have "2.4x the compaction ratio" of 10 nm. This puts the 7-nanometer node at around 202-250 million transistors per square millimeter.

https://en.wikichip.org/wiki/7_nm_lithography_process#P1276

tpmx• 6 years ago

Foundry sale price of $238/chip seems way too high.

See e.g. https://www.cultofmac.com/658650/iphone-11-pro-max-productio...

Apple A13 processor that (is) supposedly is priced at $64.

grenoire• 6 years ago

Somebody has to do it and Apple has the cash, I think they can afford to.

samatman3• 6 years ago

That is apparently the price to assure that Apple is the only purveyor in town with a 5nm process chip.

Worth it? Apple thinks so.

wmf4• 6 years ago

Apple doesn't have an exclusive on 5 nm; it's also being used by Kirin 9000, Snapdragon 875, some Exynos, and a future Dimensity SoC.

twoodfin• 6 years ago

Yeah, that $238/chip figure can't possibly be right. Apple's putting this chip in a $700 phone with at least a 50% margin. They're not blowing more than half the BoM on the SoC.

gruez• 6 years ago

The $238/chip figure probably isn't for the A14 specifically, considering that it's a chart from an unrelated report[1]

The model is based on an imaginary 5nm chip the size of Nvidia's P100 GPU (610 mm2, 90.7 billion transistors at 148.2 MTr/mm2).

[1] https://cset.georgetown.edu/wp-content/uploads/AI-Chips%E2%8...

throwaway4good3• 6 years ago

In 2004 the cost pr. chip was $2,433 which doesn't make sense either.

Is there a way to read the original report that this post was based upon?

tpowell• 6 years ago

I was curious just how many chips per wafer they net. From this 2018 article[1], it appears to be ~530 at 5nm, which would be $32ea if that yield is accurate. The same article estimated 7nm chips came out to $18ea.

Apparently, R&D spend went up 50% from 7nm to 5nm. I'm curious to see how many flavors of the A14 Apple cooks up given the comparatively high die cost.

[1] https://wccftech.com/apple-5nm-3nm-cost-transistors/

wincy2• 6 years ago

This might be one of the reasons they're transitioning to Apple Silicon, as it will allow them to justify the raising R&D costs over a wider array of products.

macintux• 6 years ago

Are Mac volume numbers even a rounding error relative to mobile devices?

ineedasername3• 6 years ago

I thought it was also interesting that cost-per-transistor had remained the same as well.

wmf4• 6 years ago

I got 656 total dies of which ~600 are good so that's $28.

https://caly-technologies.com/die-yield-calculator/

topspin4• 6 years ago

I really appreciate this analysis and the straightforward top line number 134e6/mm^2. The usual "node" figure is utterly meaningless; an electrical engineer couldn't care less about "feature" size (whatever that means.) What is the count of discrete components in a given area? There are 40 billion 5nm (the supposed "node" of these chips) squares in a millimeter of area. That's two orders of magnitude more dense than 134 million.

The meaningful achievement is how many discrete electrical components are composed into a given area. Not some arbitrary dimension of some cherry picked subset of these components.

moonchild• 6 years ago

The meaningful achievement is how many discrete electrical components are composed into a given area. Not some arbitrary dimension of some cherry picked subset of these components.

I disagree. The meaningful achievement is how power-efficient, fast, and cheap you can make a given chip. (Secondarily, how small and how durable wrt cosmic rays; but for most purposes these are not super important.)

If that follows as a result of many discrete electrical components being packed into a small area, great; but the latter isn't intrinsically interesting.

topspin4• 6 years ago

If that follows

Efficiency, performance and cost are strongly related to density. Price less so; that's a function of supply and demand.

est31• 6 years ago

The issue with power efficiency, speed, and price is that it's even harder to measure than transistor density. Furthermore, I think metrics that measure the technological progress of the silicon manufacturing are a useful tool for enriching comparisons of chips. Yes, numbers like cache sizes (or transistor density) aren't what people ultimately need/want, they want speed, but it still helps them compare chips. Improvements of the underlying process alone could lead to improvements of power efficiency, speed, and price.

eightysixfour3• 6 years ago

The meaningful achievement is how many discrete electrical components are composed into a given area.

Is average over an area the meaningful achievement or is the meaningful achievement the smallest individual gate length? Neither are super useful without additional context.

hinkley6• 6 years ago

Let's say I made a tiny transistor but to avoid leakage/interference or melting the transistor, I had to surround it by a bunch of empty silicon. There are lots and lots of cases where this could not be called a success.

I hesitate to say there are none, because I'm sure some task that is highly sensitive to latency might potentially benefit, but if you build the whole chip that way, it would actually be a regression.

coherentpony2• 6 years ago

These things aren't _really_ two-dimensional. They're not really three-dimensional either, but they are objects built out of layers of two-dimensional things. When you measure number of transistors per unit area you will inevitably see something more dense than the "number of 5nm square in a millimeter of area".

It's the silicon equivalent of measuring one's BMI.

hinkley6• 6 years ago

Video games used to call their pseudo-3d display 2.5D, or if they were feeling fancy, isomorphic.

There is a little freedom in the Z axis, but not very much. But if speed of light matters to performance, then a chip design that increases the z axis decreases the euclidean distance between any two gates, which should (or at least could) matter to performance, right?

hinkley6• 6 years ago

A cycle or two ago I asked this same question. Some people seemed to think that such a number would be gamed, but if that's a valid barrier to entry then we will never accomplish anything again, really.

As long as the measure is in mm^2, not mm^3, I think (hope?) that would avoid any perverse incentives against breakthroughs that allow you to add more layers to a chip and still maintain yields.

narrator• 6 years ago

The funny thing is is this isn't really Apple's achievement. It's TSMC's achievement. It's also Intel's failure in that they failed to get a similar process working on schedule.

desiarnezjr2• 6 years ago

Yes, but Qualcomm, Nvidia, AMD and countless others use the same fabs or at least have access to the same fabs. It's Apple's engineering and design.

robocat• 6 years ago

I think you are using black and white thinking: both deserve praise.

Delivering a CPU on a new node process is not a trivial achievement, along with the significant design changes required to achieve the potential gains of the node. Neither is Apple’s business ability to lock in x months of exclusive use of that node. Apple have done an amazing job here, hand in hand with TSMC.

2muchcoffeeman• 6 years ago

Comments like these and the ensuing arguments are funny. Especially considering the supposed audience.

What makes you think coordinating something like this is an easy task for anyone? As if you could ever distil this down to the efforts of a single organisation.

Nokinside• 6 years ago

straightforward top line number 134e6/mm^2

Even that number is not so straightforward.

Tr/mm^2 = 0.6 * (NAND2 Tr)/mm^2 + 0.4 * (Scan Flip-fop Tr)/mm2

m4633• 6 years ago

"As of 2019, the highest transistor count in any IC chip is Samsung's 1 TB eUFS (3D-stacked) V-NAND flash memory chip, with 2 trillion floating-gate MOSFETs (4 bits per transistor)." [1]

How about bit count? (at 4 bits per transistor)

[1] https://en.wikipedia.org/wiki/Transistor_count

ineedasername3• 6 years ago

What's the relative heat dissipation between logic & SRAM on a chip? The article talks about layering as a potential way forward for SRAM, but that would come with more complex TDP management, unless SRAM isn't burning watts at the same rate as the rest of the chip.

Tuna-Fish• 6 years ago

SRAM can potentially use very little power on modern processes, depending on how fast you want to be able to access it.

If you are just making a relatively low-speed L3, getting rid of the heat produced in the SRAM itself will never be a problem. In general, the problem in SRAM layered on chip is considered to be that the stacked dies are a very good insulator, so the hot active die on the bottom will have heat dissipation problems.

Symmetry3• 6 years ago

There's also smaller, but less efficient and slower 6 transistors cells versus larger but more efficient and faster 8 transistor cells to compare.

nimish• 6 years ago

This is about 35% denser than intel 10nm, and not a theoretical number.

baron816• 6 years ago

Would hate to be the guy that had to count all those transistors.

microtherion• 6 years ago

It's not that hard: You just count the pins and divide by 3.

m4633• 6 years ago

"As of 2019, the highest transistor count in any IC chip is Samsung's 1 TB eUFS (3D-stacked) V-NAND flash memory chip, with 2 trillion floating-gate MOSFETs (4 bits per transistor)."

At 4 bits per transistor and 3 pins, how do you count the samsung bits? :)

ChuckMcM4• 6 years ago

I found this to be a pretty confusing article. I get that they are analyzing the new node, which is great, but the editorializing seems a bit premature to me.

I also don't think the author understood the TMSC presentation. TMSC clearly said that is used a "model" of a typical SOC of 60% logic, 30% SRAM, and 10% analog. Then they said that for each category of thing, you could expect 1.8x, 1.35x, and 1.2x of shrink. If you do the math, that means an overall shrink for a 'typical' SOC that conforms to their model would be 1.57x (approximately).

That Apple achieved 1.49x would suggest they got 95% of the process shrink effectiveness.

Then there is the cost per die and thus cost per transistor discussion. It is important to remember that this is likely the most expensive these wafers will ever be. The reasoning for that statement is that during a process node life-cycle the cost per wafer is set initially to capture "early movers" (who value density over cost). Much like any product where competition will emerge "later" there is a window early on to recapture value which can pay back your R&D and capital equipment investments. As a result the vendor sets the price as high as possible to make that repayment happen as quickly as possible. Once paid back, the price provides profit as long as it can be supported in the presence of other competitors (in this case, I would guess that role is played by Samsung). The GSA uses to publish price surveys of wafers on various nodes over time but they don't seem to do that any more. Anyway, so the cost per transistor will go down from this point but how much depends on how much margin is in the current wafer price.

So I agree that the cost per transistor is not going down as quickly as it has in the past, and its possible that this node may not get to be as low as the previous node. I'm curious how it compares when you look at 7nm introduction price per transistor vs todays price per transistor. And if you get the same ramp with the 5nm node what that would mean.

londons_explore• 6 years ago

TSMC has a monopoly on the highest performance processes - so the price won't drop till there is competition. Seeing how the competition is falling behind, that will be a while...

MangoCoffee• 6 years ago

TSMC is about to win on packaging too

https://www.digitimes.com/news/a20201026VL200.html

ChuckMcM4• 6 years ago

I was referring to this: https://www.anandtech.com/show/15538/samsung-starts-mass-pro...

Which has Samsung in production of their 7nm node this year as well.

thornjm• 6 years ago

The column is explicitly labelled "effective vs theoretical" though. There is nothing misleading there.

ChuckMcM4• 6 years ago

This is where I believe the author goes astray: "Despite TSMC claiming a 1.8x shrink for N5, Apple only achieves a 1.49x shrink."

TSMC does NOT say they have a 1.8x shrink for N5, they say for LOGIC you can get that, but for SRAM and Analog the results are 1.35x and 1.2x. Had they summed that together for a "typical SOC", which they also discuss (and one presumes that Apple makes typical SOCs) then the "theoretical" shrink is 1.57x for SoCs.

The challenge is that whereas at one time the node size was that of a "gate" (which could be 4 transistors), in a marketing race for smaller numbers fabs started emphasizing "feature" size.

Because of this change, the "theoretical shrink" is a function of what kinds of circuits you're putting down. Pure logic? You get one number, two gates connected together for a flip-flop, you get another number, a voltage regulator, or ADC filter, you get another number.

So doing the analysis the author claims to do, can ONLY be done if you know what percentage of the part you are making on the new process is what. I am under the impression that they missed that.

hedgehog• 6 years ago

Apple is also probably using more SRAM than the "typical SOC", for example the A13 has much more cache than say the Snapdragon 855. I don't know the relative die areas but that would let you make a decent estimate.

disillusionmnt• 6 years ago

Was I the only one disappointed in the decreasing die size? In our solid state past, it was about cramming more in there. All this cost-cutting leaving gaps... it wouldn’t pass the Jobs’ fish tank test.

ksec• 6 years ago

And the economic model now requires Leading Edge Fab to capture those value in a longer period of time. What used to be two years will be lengthen closer to three.

I'm curious how it compares when you look at 7nm introduction price per transistor vs todays price per transistor. And if you get the same ramp with the 5nm node what that would mean.

First Gen N7 being ~10K+ per wafer while N5 being around ~13K with higher yield compare to N7 in the same stage. So N5 should still be cheaper.

m3at• 6 years ago

The article quote ~17K for N5, do you have an other price reference or was it just a typo?

amelius2• 6 years ago

Isn't this mostly TSMC's achievement?

Can't their other clients reach the same density?

Buraksr2• 6 years ago

Yes and no. TSMC's process node gives some hard upper limit to what can be built, but whether you can make your design that compact is an open question.

One consideration is that while we think of each transistor as individual and isolated, in reality they are simply wells of n and p type silicon with some oxides and metal thrown in. Because of this we can get unwanted parasitic components and latches. A BJT transistor for example is just a pattern of three silicon types, so it is somewhat inevitable that these will occur, whether they cause issues, and to what extent depends on the design.

Packing everything as tight as possible gives noise concerns, thermal concerns, signal integrity issues ect.

This is not to devalue the achievement of TSMC, but to state that design work is still a work as well.

[1] https://ieeexplore.ieee.org/document/145696

amelius2• 6 years ago

Ok, but doesn't Apple use EDA tools for that? Or did they develop their own?

jagger27• 6 years ago

I was curious and looked up how this compared to the computer my family had 20 years ago: a Dell XPS tower with a Pentium III. The A14 has more than 1,000x as many transistors as what Intel was doing 20 years ago on a 128mm^2 die. Pretty incredible.

toddmatthews• 6 years ago

Had that same computer when I was a senior in high school 1999

hmottestad3• 6 years ago

As someone with an 8 year old MacBook Pro that isn’t all that much slower than my 2019 16”.... I am so glad Apple is still pushing the envelope.

Back in the old days we used to get a doubling of performance every year or two. Then Intel got into trouble and has been producing the same chips for what 4-5 years? Essentially just minor changes.

It’s not really Apple’s fault that the rest of the industry is lagging so badly on performance. My Nokia was fast enough, of course no one “needs” a faster phone. But it only appears so much faster because the rest of the industry has stagnated.

Had Intel kept their tick-tock cadence then these new "faster” phones would hardly be considered fast.

titzer• 6 years ago

Blaming Intel for the end to frequency scaling is overblown. The reality is that the entire field started to hit limitations imposed by physics on the current silicon trajectory. While transistors kept (and keep) getting smaller, it's diminishing returns squeezing clockspeed and single-core performance out of it. Instead, everything has been going into scaling horizontally with more cores and more cache.

hmottestad3• 6 years ago

The A14 scores 50% higher single core performance in geekbench compared to the i7 in my 16”MacBook Pro from 2019.

Also the current gen high end laptop CPUs from Intel are still 14nm. Which they introduced in 2015 with broadwell [1]. Others have shown that’s it’s very possible to scale beyond 14nm, so there is good reason to blame Intel here!

1. https://ark.intel.com/content/www/us/en/ark/products/87719/i...

raydev2• 6 years ago

My 2013 high end 15" MBP gets pretty hot when I'm watching 1080p or higher videos. Chrome+YouTube is even worse, it even drops frames. Compiling Swift is even worse than that.

I have a work-provided 16" MBP that does all these things effortlessly.

zachberger• 6 years ago

I have an early 2013 MBP and its still a champ, none of those problems.

I'd suggest popping off the bottom and cleaning out the dust, I do this about once a year.

Dylan168074• 6 years ago

Are they using the same amount of hardware acceleration?

If one has support for VP9 and one doesn't, then most of that is not because the cores changed in performance, it's because the video decoder got rearranged.

dmitshur• 6 years ago

Another consideration when making this kind of a comparison between an older laptop and a newer one is how much dust or debris are in each of them. If it’s an unequal amount, that’ll skew the spec comparison.

hmottestad3• 6 years ago

I don’t use Chrome much. Safari runs YouTube perfectly fine, even while running benchmarks for a dev project I work on at home.

throwaway4good3• 6 years ago

For comparison. The Kirin 9000 (which includes a 5G modem) appears to have 15.3B transistors, the A14 has 11.8B transistors.

https://en.wikipedia.org/wiki/Transistor_count

Has a big table listing a number of historical CPUs.

hellokaushik• 6 years ago

Nice

Apple’s A14 Packs 134M Transistors/mm²

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