Why is Apple's M1 chip so fast?

https://erik-engheim.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2

768 628 6 years ago

erik-engheim.medium.com

What are the technical reasons why the M1 chip is so fast. Does Apple use any exotic tricks? Can Intel and AMD do the same trick in their chips?

Justsignedup• 6 years ago

Sounds like apple made multiple specialized processors for specific tasks, built a motherboard around that, and cooked all that into the OS. It's a bit of a cheat since they aren't building a generic computer architecture, but a very very specialized one.

This is different with say Windows architecture. In windows vendors work on generic cpus/gpus/motherboards. Some hardware isn't exactly available or uniformally accessible due to drivers and such. This is kind of the huge benefit Apple has by creating the hardware, OS, drivers, languages and libraries.

zepto6• 6 years ago

This is what they do with everything. It is the reason for vertical integration.

Calling it ‘a cheat’ is somewhat weird.

The point is that a general purpose CPU is a bad solution for a personal computer.

The neural engine is about processing the ambiguous world that humans occupy so that the human doesn’t have to translate so much for the computer.

The GPU is about communicating visually with humans.

eng2prog5• 6 years ago

Today all of this is exciting, but I have a bad feeling this is going to slide Apple towards a low performance future.

They Apple'd themselves and locked themselves in.

In 2 years, secrets aside, Apple would need to beat all 3 big dogs to be the top. How long can they sustain that?

sliken24• 6 years ago

Apple did optimize for some common use cases, reference counting (as used by objc++), javascript tweaks, and for emulation for rosetta2. However they also made a great general purpose CPU that will run many standard codes impressively quickly for impressively little power.

NobodyNada• 6 years ago

If that were the case, though, we would expect to see performance gains only in areas the M1 is specialized for -- but that's not what we see. The M1's GeekBench scores are impressively high, and general-computing workloads like compiling code are very fast as well, indicating that the M1 is fast in general, not just for specific tasks.

There's been a lot of hype about things like "specialized hardware for NSObjects," but AFAIK that's more of a flawed/outdated design on Intel' side than a specialization on Apple's: the "magic" is really just ARM's weaker & more modern memory consistency model, which makes things like reference counting substantially faster.

socialdemocrat6• 6 years ago

Yeah and I think it will be quite interesting to see in the years ahead how this kind of highly specialized approach to computing will stack up against the more generic wintel approach, and how customers will respond.

Customers may end up with having the choice between a very high performance system at competitive prices, vs an open architecture which has more flexibility in what you add, but which will ultimately cost more and have worse performance.

You can see this play out in different markets. Just look at Tesla e.g. They are taking the Apple approach to car making with full vertical integration. They are doing everything from making their own alloys to creating their own machine learning hardware.

I think we are at some kind of paradigm shift and the old guard has been caught off guard.

stefan_• 6 years ago

They use this one trick that AMD and others hate: they paid TSMC to use up all of their 5nm capacity.

GloriousKoji• 6 years ago

I have an anecdote possibly related to this. I work for a semiconductor company and we were in pretty good standing with TSMC. All of a sudden we were informed we should longer contact the usual engineers them and a new team of engineers was assigned to us. It was very clear the new staff was their B-team. Rumor around the office the A-team went to support Apple.

amq• 6 years ago

I see two main reasons:

- 5nm process (1.8x the density of 7nm [1])

- unified memory directly on the SoC

[1] https://hexus.net/tech/news/industry/130175-tsmc-5nm-will-im...

kllrnohj17• 6 years ago

Unified memory is old, every CPU with an integrated GPU is on unified memory. It's not doing anything at all for M1's general performance.

The main reason for M1's performance is just that Apple managed to get an 8-wide CPU to work & be fed. That's it. That's the entirety of the story of the M1. Apple got 8-wide to work, while Intel & AMD are still 4-wide. ARM's fixed length instructions are helping a ton there, but Apple also put in work to feed it.

All the other shit about specialized units & unified memory & vertical integration is all irrelevant and mostly wrong. The existing Intel Macbook Airs are all unified memory with specialized hardware units for specialized tasks, too (Intel QuickSync is 9 years old now - dedicated silicon for the specialized task of video encoding). Apple did absolutely nothing new or interesting on that front. Other than marketing. They are magic at marketing. And also magic at making a super wide CPU front-end, with really good cache latency numbers.

jayd16• 6 years ago

Is this a bot? This is just lifted from the article verbatim.

Do I get my Turing tester badge?

chess_buster• 6 years ago

Did you read the article? Does not seem like it.

gfody• 6 years ago

IIRC Apple got some exotic automated optimization tech when when they acquired PA Semi - I think it was mentioned in the Steve Jobs biography. The A chips have always been impressive and the timing lines up.

jonplackett8• 6 years ago

read the article!

aey3• 6 years ago

Because of the 12MB L2 cache as the point of unification. 865 snapdragon has a 4mb L3. Same as my recent intel MacBook.

Apple can use at least as much more die as amd/qcom/intel’s profit margin.

periya• 6 years ago

Also being on TSMC5 on top of significant micro architecture improvements ; ~630 instruction deep ROB, ability to queue ~150 outstanding load instruction and ~100 outstanding stores and huge TLBs which reduces swapping the anandtech article does a great job going into explaining this.

aey3• 6 years ago

All that helps, but if you look at the die you are going to see a massive 12MB L2 with a bunch of routing to all the L1s. That’s where the majority of the cost is going vs any other chip.

bee_rider2• 6 years ago

Intel probably should have dropped their profit margin just to prevent this embarrassment. This is the foot in the door. Or through the door.

kllrnohj17• 6 years ago

If cache size was the answer then Intel would have already stuck more on their CPUs, and AMD's 32MB on Zen3 would be carrying far more weight against the M1 than it is.

Bigger caches mean higher latency caches, it's not strictly a matter of bigger is better.

aey3• 6 years ago

It’s an L2, amd zen has 2x16mb L3s, with a wacky point of unification. L3 is muuuuch slower than L2.

Apple’s L2 is huge and is the PoU for all the cores. I wouldn’t be surprised if it has direct routing to all the L1s since they are so small. 5nm doesn’t hurt.

hardwaregeek• 6 years ago

Ugh. Any way around the requirement to sign in with Google? Very frustrating that this is required to read a damn blog post.

minddeep2• 6 years ago

Incognito mode of your browser

whyrusleeping• 6 years ago

Use an incognito tab

suprfsat• 6 years ago

Block javascript from medium.com

ducttapecrown• 6 years ago

Using a JavaScript toggle button also works.

mtzaldo• 6 years ago

disable third-party cookies in your browser

jonplackett8• 6 years ago

I'm never sure if I like or hate when a site's adblock/article limit/sign in requirement etc is so easy to circumvent.

On the one hand it's good for me, on the other I feel like, couldn't you have put in a bit more effort? if you're going to make it that easy why bother?

(I know it's just because most people don't realise)

jmnicolas• 6 years ago

I use uBlock origin. Never saw any signing form.

nathanasmith• 6 years ago

I use the excellent Readium bookmarklet[0]. Drag it to your bookmarks bar and whenever you encounter a Medium article you can't read, just click it and problem solved.

[0]https://sugoidesune.github.io/readium/

addaon• 6 years ago

My recollection is that when P. A. Semi was acquired by Apple, a major part of their "secret sauce" was a custom cell library. And then Intrinsity, a few years later, also seemed to be using custom cells on Samsung's process. Is this recollection / understanding correct? Is Apple still using custom cell libraries rather than TSMC's standard library?

ahupp2• 6 years ago

What does "cell" mean in this context?

robert_foss5• 6 years ago

https://en.wikipedia.org/wiki/Standard_cell

dreamcompiler2• 6 years ago

It's one level of abstraction above the transistor level; in other words gates and sets of gates. Designing at the raw transistor level is tedious, time-consuming, and requires specialized knowledge of low-level electrical and physics characteristics. When you design with standard cells, you only have to think about the logic functionality.

https://en.wikipedia.org/wiki/Standard_cell

The parent's question is about whether Apple really did do some of the designing at the transistor level by designing their own cells, rather than using a standard library. This could give them an edge that ordinary users of the standard library wouldn't have.

morganw• 6 years ago

https://en.wikipedia.org/wiki/Standard_cell#Library

"A standard cell library is a collection of low-level electronic logic functions such as AND, OR, INVERT, flip-flops, latches, and buffers. "

I think SRAMs are also built of standard cells & there can be a lot of flexibility to improve on the fab's library, particularly with multiple ports for caches.

Geee• 6 years ago

It's the basic low-level building block of an integrated circuit.[0]

[0] https://en.wikipedia.org/wiki/Standard_cell

greyhair8• 6 years ago

The team at P.A.Semi was the team that developed the DEC Alpha and the DEC StrongARM. After DEC folded, they went on to develop PowerPC based chips. Shortly after they completed their PowerPC design they were bought up by Apple.

https://en.wikipedia.org/wiki/P.A._Semi

klelatti4• 6 years ago

Ironically StrongARM was sold to Intel who developed it as XScale before selling to Marvell.

minddeep2• 6 years ago

Great explanation and also a good read on challenges Intel and AMD will face going forward. I am wondering if any of the windows / linux laptop makers will follow suit? Or will it be too hard to use the generic windows / linux and optimize it for custom built hardware?

eng2prog5• 6 years ago

Why bother? Computing is blazing fast already. Anything that is slow should use multi threading.

There's a reason most computers compromise on the processor performance, we don't need it. Take that extra few hundred and give me more ram and a better video card.

jonplackett8• 6 years ago

Because battery life.

vmchale4• 6 years ago

Hope so. I could happily use arm chips on mobile.

qayxc• 6 years ago

I am wondering if any of the windows / linux laptop makers will follow suit?

The article was actually spot-on in giving a reason why this won't be the case: AMD, Intel, and NVIDIA aren't going to license any of their IP to the likes of Dell, HP, MSI, Toshiba, Lenovo, TongFeng or ASUS.

Only NVIDIA and Qualcomm are left in the ARM SoC market (in terms of proprietary chip designs) since Samsung shut down their custom CPU design department end of last year. Neither of the two is competitive in terms of performance with Apple's custom chips and their SoCs are OK for SBCs, tablets, and Chromebook-level hardware but in no way competitive with even mid-range offerings from AMD and Intel.

Another factor is vendor lock-in. Since M1-style ARM-based SoCs wouldn't allow for discrete GPUs and RAM upgrades, creating a carefully segmented range of SKUs would be next to impossible. Even Apple struggles to do so as seen by the virtually non-existent differentiation between the M1 Macbook Air and -Pro.

AMD- and Intel-based systems allow OEMs to create bespoke product lines for each target market: NVIDIA Quadros and 32+GB of RAM for CAD/CAM and design work, powerful systems for gamers, CPUs with "pro"-features for businesses, etc.

An SoC is the same for all products. Sure, you can do some minimal differentiation by disabling a core or two, binning and cooling, but in the end there's very little practical difference between an SoC with 7 or 8 GPU cores... I'm pretty sure the MBA will cannibalise sales of the MBP big time for this exact reason.

benjaminl• 6 years ago

Unlike what has been said on Twitter the answer to why the M1 is fast isn’t due to technical tricks, but due to Apple throwing a lot of hardware at the problem.

The M1 is really wide (8 wide decode) and has a lot of execution units. It has a huge 630 deep reorder buffer to keep them all filled, multiple large caches and a lot of memory bandwidth.

It is just a monster of a chip, well designed balanced and executed.

BTW this isn’t really new. Apple has been making incremental progress year by year on these processor for their A-series chips. Just nobody believed those Geekbench benchmarks showing that in short benchmarks your phone could be faster than your laptop. Well turns out that given the right cooling solution those benchmarks were accurate.

Anandtech has a wonderful deep dive into the processor architecture.

https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de...

Edit: I didn’t mean to disparage Apple or the M1 by saying that Apple threw hardware at the problem. That Apple was able to keep power low with such a wide chip is extremely impressive and speaks to how finely tuned the chip is. I was trying to say that Apple got the results they did the hard way by advancing every aspect of the chip.

vmchale4• 6 years ago

Just nobody believed those Geekbench benchmarks showing that in short benchmarks your phone could be faster than your laptop.

I saw a paper on (I think?) SMT solvers on iPhone. Turned out to be faster than laptops, I kind of brushed over it as irrelevant at the time.

fiddlerwoaroof2• 6 years ago

https://www.cs.utexas.edu/~bornholt/post/z3-iphone.html

FpUser4• 6 years ago

I did believe those benchmarks. I also knew that sustainable load at those speeds if not throttled down would just melt the thing so yes they were irrelevant.

Kolja2• 6 years ago

Just nobody believed those Geekbench benchmarks showing that in short benchmarks your phone could be faster than your laptop.

Except for a lot of the Apple-centric journalists and podcasters, who have been imagining for years how fast a desktop built on these already-very-fast-when-passively-cooled chips could be.

Not that that matters very much when experienced and real-world workload performance suffers, but as far as I can tell, the M1 is no slouch in that respect either.

fiddlerwoaroof2• 6 years ago

Yeah, Apple’s CPUs have been doing really well for a while now: https://www.cs.utexas.edu/~bornholt/post/z3-iphone.html

pletnes• 6 years ago

I heard 10 years ago, or whatever, that the ipad 2 had the most power efficient CPU available, period. This was told at a keynote by an HPC scientist who cannot be said to be a «apple journalist». Apple have been doing well for a very long time and I’ve expected this moment since that keynote, basically.

saberience• 6 years ago

I find it interesting you use this kind of disparaging tone when discussing Apple Silicon. I also find it interesting that you consider having a wide decoder not as a technical trick but as "throwing hardware at the problem."

However you try and spin it, what it comes down to is this, Apple is somehow designing more performant processors than every other company in the world and we should acknowledge they are beating the "traditional" chip designing companies handily while being new at the game.

If it's as easy as "throwing hardware" at the problem, then Intel and AMD and Samsung etc should have no problem beating Apple right?

robert_foss5• 6 years ago

Apple is throwing money at the problem. IC size is directly proportional to cost.

They couldn't sell a chip like this at a cost-competitive price on the open market against AMD/Intel products.

kstrauser• 6 years ago

I interpreted that differently: they used good engineering to make a speed demon of a chip, not some magic trick that's only good in benchmarks and not real world usage. I don't think it was disparaging at all.

est312• 6 years ago

They didn't just throw hardware at the problem, but also talent. Something that is way more scarce.

bigdict2• 6 years ago

Yeah, it's like saying "well all Apple is doing is throwing good engineering at the problem".

All they've really done is taken an advanced process, coupled it with a powerful architecture they've been iteratively improving on for years, and thrown it at software that has been codesigned to work really well on those chips.

Yeesh!

libria2• 6 years ago

Just to quantify your adjectives, per the Anandtech article:

The M1 is really wide (8 wide decode)

In contrast to x86 CPUs which are 4 wide decode.

It has a huge 630 deep reorder buffer

By comparison, Intel Sunny/Willow has 352.

natchy• 6 years ago

So Intel and AMD are capable of building a chip like this, but the ambitious size meant it was more economically feasible for Apple to build it themselves?

(Not a hardware guy)

trynumber9• 6 years ago

But in one x86 instruction you often have more complex operations. Isn't that part of the reason why Sunny Cove has only 4 wide decode but still the decoders can yield 6 micro-ops per cycle? That single stat makes it look worse than it is in reality, I think.

pclmulqdq5• 6 years ago

Zen 2 has has 8-wide issue in many places, and Ice Lake moves up to 6-wide. Intel/AMD have had 4-wide decode and issue width for 10 years and I'm glad they're moving to wider machines.

Edited "decode" to "issue" for clarity.

sliken24• 6 years ago

You mention most of the big changes, except one. Assuming a random (but TLB friendly) pattern the M1 manages a latency of around 30-33ns to main memory, about half of what I've seen anywhere else. Impressive.

Maybe motherboards should stop coming with dimms and use the apple approach to get great bandwidth and latency and come in 16, 32, and 64GB varieties by soldering LPDDR4x on the motherboard.

aldanor• 6 years ago

Or maybe use the best of both worlds, with soldered-in ultra fast ram, plus large amount of dimm ram.

Same as you can have a storage driver and a smaller nvme.

impassionedrule• 6 years ago

We should definitely not continue Apple's approach of soldering every damn component, even if it comes at the cost of performance

formerly_proven• 6 years ago

Latencies like this are doable with a lot of tuning on Intel CPUs; out of the box you'll get to the 40s with fast memory. And those CPUs have three cache levels instead of two...

A good old-fashioned 2010-era gaming PC would already get down to around 50 ns levels.

It's definitely really good, but considering it's rather fast RAM (DDR4 4266 CL16) and doesn't have L3 it's not that surprising.

epakai• 6 years ago

Bandwidth is comparable with other high-end laptop chipsets (I've seen 60-68 GB/s quoted, and recent Ryzens are 68 GB/s). Is the on-chip latency a big factor in the single core performance?

brandmeyer2• 6 years ago

Assuming a random (but TLB friendly) pattern the M1 manages a latency of around 30-33ns to main memory.

This, right here. It also helps that the L1D is a whopping 128 kB and only 3 cycles of load-use latency.

myrandomcomment3• 6 years ago

This reminds me of the Amiga which had FastRAM and ChipRAM. It was all main memory, but the ChipRAM could be directly addressed by all the co-processor HW in the Amiga and the FastRAM could not.

It would be sort of interesting for Intel/AMD to do something like this where they have 16GB on the CPU and the OS has the knowledge to see it differently from external RAM.

Apple is going to have to do this for their real "Pro" side devices as getting 1TB on the Mx will be a non-starter. I would expect to see the M2 (or whatever) with a large amount of the basic on chip RAM and then an external RAM bus also.

threeseed2• 6 years ago

Memory usage has definitely stalled over the last decade as more applications move to the web or mobile devices.

There's just nothing driving most people to have more than 8/16GB of RAM and even photo/video editing has been shown to be a breeze on the 8GB MacBook Air.

I wouldn't be surprised to see laptops move to soldered RAM and SSDs.

FpUser4• 6 years ago

"Maybe motherboards should stop coming with dimms and use the apple approach to get great bandwidth and latency and come in 16, 32, and 64GB varieties by soldering LPDDR4x on the motherboard."

I prefer the upgradeability.

kllrnohj17• 6 years ago

Assuming a random (but TLB friendly) pattern the M1 manages a latency of around 30-33ns to main memory, about half of what I've seen anywhere else. Impressive.

Cite your number please. Anandtech measured M1's memory latency at 96ns, worse than either a modern Intel or AMD CPU: "In terms of memory latency, we’re seeing a (rather expected) reduction compared to the A14, measuring 96ns at 128MB full random test depth, compared to 102ns on the A14."

https://www.anandtech.com/show/16252/mac-mini-apple-m1-teste...

vs. "In the DRAM region, we’re measuring 78.8ns on the 5950X"

https://www.anandtech.com/show/16214/amd-zen-3-ryzen-deep-di...

ori_b• 6 years ago

The next question: What prevents Intel or AMD from doing this on their processors?

jonplackett8• 6 years ago

The article specifically answers this:

- x86 instruction set can't be queued up as easily because instructions have different lengths - 4 decoders max, while Apple has 8 and could go higher.

- Business model does not allow this kind of integration.

rcthompson• 6 years ago

The article answers this: x86 has variable-sized instructions, which makes decoding much more complex and hard to parallelize since you don't know the starting point of each instruction until you read it.

crystaln• 6 years ago

Seems like backward compatibility completely rules this out. Apple can provide tools and clear migration paths because the chips are only used in their systems. Intel chips are used everywhere, and Intel has no visibility.

gigatexal3• 6 years ago

Yeah the article is interesting I just like knowing that Apple will keep iterating and the performance gap between Apple Silicon and x86 will continue to grow. I keep spec'ing out an Apple M1 Mac mini only to not pull the trigger because I am curious what an M2 will hold.

2muchcoffeeman2• 6 years ago

I think they old adage, “don’t buy first generation Apple products” applies here. Seems sensible to wait to see where this goes.

libria2• 6 years ago

Hah, won't this perpetuate? Whenever M(N) is released M(N+1) will be on the horizon with even greater promise.

eatmyshorts• 6 years ago

The rumors I've read so far is that the next chip will be the M1-X, and will be a 12-core CPU, with 8 "high performance" cores and 4 "efficiency" cores, and will be released in a 16" MBP. The current M1, by contrast, has an 8-core CPU (4 HP cores and 4 efficiency cores).

rootusrootus• 6 years ago

The nice thing about Apple hardware resale value is that you can just buy now and upgrade later. I just unloaded a five year old MBP for a lot more than I'd ever have gotten for a five year old PC laptop. Ordered myself a fancy new M1 laptop, and if M1X/M2/whatever-it-is-called is substantially better, then I'll just trade it in on a new model. There's always a new hotness coming next year.

PeterisP2• 6 years ago

Are they really throwing more hardware at the problem?

The die size for the whole M1 SoC is comparable to or even smaller than Intel processors, and the vast majority of that SoC is non-CPU related stuff, the CPU cores/cache/etc seem to be at most 20% of that die - though a more dense die because of the 5nm process. This also seems to imply that the 'budget' of number of transistors for that CPU-part of the SoC is also comparable to previous Intel processors, not a significant increase. (Assuming 20% of the 16b transistors in M1 is CPU part, it would be 3-ish billion transistors, and the Intel does not seem to publish transistor counts but I believe it's more than that for the Intel i9 chips in last year's macbookspro)

Perhaps my estimates are wrong, but it seems that they aren't throwing more hardware, but managing to achieve much more with the same "amount of hardware" because it is substantially different.

temac4• 6 years ago

Well you don't have any of the AVX512 nonsense, but probably the OOO of the M1 uses more transistors than on an Intel chip. And Google tells me that a quad core i7-7700K has 2.16 B.

throwarchitect3• 6 years ago

the M1 is fast isn’t due to technical tricks, but due to Apple throwing a lot of hardware at the problem.

Apple threw more hardware at the problem and they lowered the frequency.

By lowering the frequency relative to AMD/Intel parts, they get two great advantages. 1) they use significantly less power and 2) they can do more work per cycle, making use of all of that extra hardware.

baybal27• 6 years ago

But Apple has a crazy 8 decoders. Not only that but the ROB is something like 3x larger. You can basically hold 3x as many instructions. No other mainstream chip maker has that many decoders in their CPUs.

The author completely misses "the baby in the water"

Yes, X86 core are HUGE, the whole of CPU is for them only.

They can afford wider decode, even though at a giant area cost (which itself would be dwarfed area cost of cache system area.)

The thing is, have more decode, and buffer will still not improve X86 perf by much

Modern X86 has good internal register, and pipeline utilisation, it's simply they don't have something to keep all of those registers busy most of the time!

What it lacks is memory, and cache I/O. All X86 chips today are I/O starved at every level. And that starvation also comes as a result of decades old X86 idiosyncrasies about how I/O should be done.

coliveira2• 6 years ago

How does I/O works differently in a M1 chip compared to x86?

rayiner7• 6 years ago

The answer of wide decode and deep reorder buffer gets much closer than the “tricks” mentioned in tweets. That still doesn’t explain how Apple built an 8-wide CPU with such deep OOO that operates on 10-15 watts.

The limit that keeps you from arbitrarily scaling up these numbers isn’t transistor count. It’s delay—how long it takes for complex circuits to settle, which drives the top clock speed. And it’s also power usage. The timing delay of many circuits inside a CPU scare super-linearly with things like decode width. For example, the delay in the decode stage itself scales quadratically with the width of the decoder: ftp://ftp.cs.wisc.edu/sohi/trs/complexity.1328.pdf (p. 15). The delay of the issue queues is quadratic both in the issue width and the depth of the queues. The delay of a full bypass network is quadratic in execution width. Decoding N instructions at a time also requires a register renaming unit that can perform register renaming for that many instructions per cycle, and the register file must have enough ports to be able to feed 2-3 operands to N different instructions per cycle. Additionally, big, multi-ported register files, deep and wide issue queues, and big reorder buffers also tend to be extremely power hungry.

On the flip side, the conventional wisdom is that most code doesn’t have enough inherent parallelism to take advantage of an 8-wide machine: https://www.realworldtech.com/shrinking-cpu/2/ (“The first sign that the party was over was diminishing returns from wider and wider superscalar designs. As CPUs went from being capable of executing 1, to 2, to 4, to even 6 instructions per cycle, the percentage of cycles during which they actually hit their full potential was dropping rapidly as both a function of increasing width and increasing clock rate.”). At the very least, such designs tend to be very application-dependent. Branch-y integer code like compilers tend to perform poorly on such wide and slow designs. The M1 by contrast manages to come close to Zen 3, which is already a high ILP CPU to begin with, despite a large clock speed deficit (3.2 ghz versus 5 ghz). And the performance seems to be robust—doing well on everything from compilation to scientific kernels. That’s really phenomenal and blows a lot of the conventional wisdom out of the water.

An insane amount of good engineering went into this CPU.

temac4• 6 years ago

An insane amount of good engineering went into this CPU.

I agree but lets not overblow the difficulties either.

For example, the delay in the decode stage itself scales quadratically with the width of the decoder.

That could be irrelevant for small enough numbers, and ARM is easier to decode than x86. So this can be very well be dominated by other things. What you cite seems to be only about decoding logical register decoding going into the renaming structures, and then for just that tiny part it even tells that "We found that, at least for the design space and technologies we explored, the quadratic component is very small relative to the other components. Hence, the delay of the decoder is linearly dependent on the issue width."

The delay of a full bypass network is quadratic in execution width.

Maybe if that's a problem don't do a full bypass network.

dropping rapidly as both a function of increasing width and increasing clock rate

Good thing that the clock rate is not too high then :p

More seriously the M1 can keep the beast fed probably because everything is dimensioned correctly, (and yes also because the clocks are not too high, but if you manage to make a wide and slow CPU that actually works well, I don't see why you would want to scale the freq too much high, given you would quickly consume like crazy, and there is only only limited headroom above 3.2GHz anyway). It obviously helps to have a gigantic OOO. So I don't really see where there is so much surprise. Esp. since we saw the progression in the A series.

To finish probably TSMC 5nm does not hurt. The competitors are on bigger nodes and have smaller structures. Coincidence? Or just like it has worked during decades already.

QuixoticQuibit• 6 years ago

I haven’t read the linked AnandTech article yet, but is there a clear answer why Apple was able to defy common comp arch wisdom (M1 has wider decode which works fine for various applications/code)?

Dylan168077• 6 years ago

For example, the delay in the decode stage itself scales quadratically with the width of the decoder: ftp://ftp.cs.wisc.edu/sohi/trs/complexity.1328.pdf (p. 15).

That's a decoder for a single field, where width of the field is the parameter it scales by. That would be instruction size or smaller, and instructions don't change size depending on how many you decode at once.

And logically once you separate the instructions you can decode in parallel in fixed time, and if all your instructions are 4 bytes then it takes no circuitry to separate them.

Also: "We found that, at least for the design space and technologies we explored, the quadratic component is very small relative to the other components. Hence, the delay of the decoder is linearly dependent on the issue width."

kllrnohj17• 6 years ago

That still doesn’t explain how Apple built an 8-wide CPU with such deep OOO that operates on 10-15 watts.

Well, because it doesn't, it's ~25 watts. And also because it runs at just 3ghz. You'll see similar power numbers from x86 CPUs at 3ghz, too. The M1's multicore performance vs. the 4800U and 4900HS demonstrate this nicely.

Tuna-Fish• 6 years ago

Your first source does not support your statement.

While there is theoretically a quadratic component, in their words:

We found that, at least for the design space and technologies we explored, the quadratic component is very small relative to the other components. Hence, the delay of the decoder is linearly dependent on the issue width.

skavi4• 6 years ago

Unlike what has been said on Twitter the answer to why the M1 is fast isn’t due to technical tricks, but due to Apple throwing a lot of hardware at the problem.

Of course Apple’s advantage is not solely due to technical tricks, but neither is it entirely, or even mostly due to an area advantage. If it were so easy, Samsung’s M1 would have been a good core.

davrosthedalek• 6 years ago

How does 8 wide decode on ARM RISC compare to 4 wide decode on x64 CISC? If, say, you'd need two RISC ops per CISC op on average, that should be the same, right?

gpderetta5• 6 years ago

Most instructions map 1:1. x86 instructions can encode memory operands potentially doubling the practical width but a) not all CPUs can decode them at full width and b) in practice compilers generate mem+ops instructions only for a (not insignificant ) minority of instructions.

So the apple to apple (pun intended) practical width difference is closer than it appear, still not as wide.

X86 machines usually target 5-6 wide rename, so that would become a bottleneck (not all instructions require rename of course). I expect that M1 has an 8-wide rename.

Edit: another limitation is that most x86 decoders can only decode 16 bytes at a time and many instructions can be very long, further limiting actual decode throughput.

On the converse the expectation is that most hot code will skip decode completely and is fed from the uop cache. This also saves power.

GeekyBear• 6 years ago

Another detail that came out today is just how beefy Apple's "little" cores are.

The performance showcased here roughly matches a 2.2GHz Cortex-A76 which is essentially 4x faster than the performance of any other mobile SoC today which relies on Cortex-A55 cores, all while using roughly the same amount of system power and having 3x the power efficiency.

https://www.anandtech.com/show/16192/the-iphone-12-review/2

fomine36• 6 years ago

Incredible. Now it should be MiDdLe core.

Sparkyte2• 6 years ago

Thank you for a better synopsis.

Bugs me so much when people don't look at the logical side of things. Tons of mac'n'knights going around downvoting and stating people are wrong that it has something to do with being a RISC processor.

While fundamentally pre 2000s things were more RISC this and CISC that the designs are more similar than ever on x86 and ARM. Just that the components are designed different to handle the different base instruction sets.

Also the article is entirely wrong about SoC Ryzen chips have been SoC since their initial inception. In fact SoC on the First APU. Those carried North Bridge components onto the CPU die.

mixmastamyk• 6 years ago

The 5nm process is a large factor as well.

gabereiser• 6 years ago

Spot on. Exactly this. It’s like pre-iPhone when people just assumed you had a laptop and a cellphone. Then Apple said “phone computer!” and changed the game. Same with iPad just less innovation shock. Meanwhile we continued to have this delineation of computer / phone while under the hood - to a hardware engineer - it’s all the same. Naturally the chips they produced for iOS-land are beasts. My phone is faster than the computer I had 5 years ago. My M1 air is just a freak of nature. On par with high end machines but passively cooled and cheaper. I’m still kinda in awe. Not a big fan of the hush hush on Apple Silicon causing us all to play catch-up for support, but that’s Apple’s track record I guess.

The M1 is all the things they learned from the A1-A12 chips (or whatever the ordering) which is over a decade of tweaking the design for efficiency (phone) while giving it power (iPad).

Taniwha2• 6 years ago

Not mentioned in the article is the downside of having really wide decoders (and why they're not likely to get much larger) - essentially the big issue in all modern CPUs is branch prediction because the cost of misprediction on a big CPU is so high - there's a rule-of-thumb that in real-world instruction streams there's a branch every 5 instructions or so ... that means that if you're decoding 8 instructions each bundle has 1 or 2 branches in it, if any are predicted taken you have to throw away the subsequent instructions - if you're decoding 16 instructions you've got 3 or 4 branches to predict, chances of having to throw something away gets higher as you go .... there's a law of diminishing returns that kicks in, and in fact has probably kicked in at 8

cbsmith• 6 years ago

...and Apple was able to throw hardware at the problem because they got TSMC's manufacturing process. When everyone else is using 5nm, let's see if any of this other stuff actually matters.

legulere• 6 years ago

It also has shared 12MB of L2 cache for the performance cores which is huge.

raxxorrax• 6 years ago

The problem is that a phone with a lightning fast CPU is rather useless with current ecosystems.

I do think there are "technical tricks" though, especially the compatibility memory mode that makes x86 emulation faster than comparable ARM chips. If you call it a trick or finesse is probably a matter of perspective.

Guthur• 6 years ago

M1 is also the only TSMC 5nm chip that is widely available and there is nothing remotely comparable from a process stand point.

burnthrow• 6 years ago

Is anybody here using one of these for serious development, and can comment on performance? On reddit there are some comments about anything Java-related being rather slow for instance.

vmchale4• 6 years ago

I'm also curious. Phoronix added clash/GHC compiler benchmarks which is relevant to my interests.

olliej• 6 years ago

If they're still not using a native JVM Java devs will be running Java under Rosetta. While rosetta can run code with JITs the performance is nowhere near AOT perf (for many reasons)

thoughtsimple5• 6 years ago

You can get M1 native Java JDK from Azul.

https://www.azul.com/downloads/zulu-community/?package=jdk

my1235• 6 years ago

There's a need to use a native Java runtime instead of one running on Rosetta (like what IntelliJ ships).

Azul Zulu is one.

seek3r2• 6 years ago

It really depends on your workflow. Also see: https://news.ycombinator.com/item?id=25238608

grey-area• 6 years ago

Depending on your definition of serious (I'd say it's serious when people pay money for it), I'm doing that and am quite happy with it. I haven't tried building any Java code though, only Go and Swift.

I'm seeing about 2x performance (eyeballing build times) of a recent Intel MBP for compiling a medium size Go codebase, running natively on arm64. The machine is noticeably faster than previous iterations for most tasks.

I've made an effort to avoid emulated code though so am running a patched version of Go 1.16 and tools. Not all tools have officially supported native versions yet, but the performance is definitely there.

thoughtsimple5• 6 years ago

I have the Azul JDK working but I haven't really done much with it. Been side-tracked by ffmpeg, QEmu and SimpleVM. But I plan to do some testing soon.

ogre_codes14• 6 years ago

While the M1 is super impressive, I'm kind of wondering how scalable the performance increases they made here are.

They moved high bandwidth RAM to be shared between the CPU & GPU, but they[1] can't just keep expanding the SoC[2] with ever larger amounts of RAM. At some point they will need external RAM in addition to the on chip RAM. Perhaps they will ship 32GB of onboard memory with external RAM being used as swap? This takes a bit away from the super-efficient design they have currently.

Likewise, putting increasingly larger GPUs onto the SoC is going to be a big challenge for higher performance/ Pro setups.

I think Apple really hit the sweet spot with the M1. I suspect the higher end chips will be faster than their Intel/ AMD counterparts, but they won't blow them out of the water the way the current MacBook Air/ MBP/ mini blow away the ~$700-2,000 PC market.

[1] I updated the text here because I'd originally commented here about the price of RAM which is largely irrelevant to the actual limitations.

[2] As has been pointed out below, the memory is not on the die with the CPU, but is in the same package. Leaving the text above intact.

dragontamer11• 6 years ago

Moving high bandwidth RAM

Its just LPDDR4. HBM is a different thing. You can tell because HBM has 1024-bits bus per chip, but LPDDR4 is just 128-bits per chip.

There's almost nothing special about the RAM, aside from it being locked to the chip and unable to be upgraded. It seems like the clockrate to the LPDDR4 is a bit higher than average, but its nothing extravagant.

How do they manage even larger amounts of RAM? Perhaps they will have external RAM in addition to the on chip RAM, with perhaps 32GB of onboard memory and the external RAM being used as swap? This takes a bit away from the super-efficient design they have currently.

They COULD just support a DIMM stick like everyone else. But Apple doesn't want to do that strategy and prefers packaging the RAM and CPU together for higher prices.

This isn't a 1024-bit bus (that requires 1024 wires, usually an interposer). This is just your standard 128-bit LPDDR4, maybe at a slightly higher clockrate than others for a slight advantage in memory.

------

In case of HBM2, you can't upgrade RAM beyond one-stack per 1024-bit bus. A GPU goes 4x wide with 4x 1024-bit busses to 4x different HBM2 stacks for a massive 4096-pin layout (!!!), that's 4096 wires connecting a GPU to individual HBM2 chips.

Hypothetically, a future GPU might go 6-stacks or 8-stacks (8192-wires), but obviously running all those wires gets more-and-more complex the bigger you go. So in practice, GPUs seem to be ~4-stacks, and then you just buy a new GPU and run the entire GPU in parallel when you need more RAM.

> Moving high bandwidth RAM to be shared between the CPU & GPU

That's not the advantage. When the L3 cache is connected between CPU and GPU, you gain a bandwidth edge in heterogenous systems. AMD / Intel have been connecting L3 caches to their iGPU solutions for over a decade now.

CPU - to DDR4 - to GPU is very slow compared to CPU - to L3 cache - to GPU. Keeping the iGPU and CPU memory-cohesive is a nifty trick, but is kind of standard at this point.

Dylan168077• 6 years ago

LPDDR4 is just 128-bits per chip.

It is? I thought it was up to 32.

ogre_codes14• 6 years ago

I'm not an expert here, just going by the articles I've read on this topic recently. That said...

Its just LPDDR4. HBM is a different thing.

Hmm, Apple refers to it as High Bandwidth Memory. The Register[1] refers to it as "High Bandwidth Memory" and also:

"This uses 4266 MT/s LPDDR4X SDRAM (synchronous DRAM) and is mounted with the SoC using a system-in-package (SiP) design."

Which implies to me that some kinds of LPDDR is indeed HBM and that what's on the M1 isn't something which can be replaced by drop in RAM.

That's not the advantage.

Hmm, again quoting The Reg here because I think it's a fairly independent source on Apple hardware.

"In other words, this memory is shared between the three different compute engines and their cores. The three don't have their own individual memory resources, which would need data moved into them."

Maybe I didn't express this clearly enough above.

AMD / Intel have been connecting L3 caches to their iGPU solutions for over a decade now.

My point above wasn't that Apple invented this idea. It was that the idea doesn't scale well. Who invented it doesn't really matter.

[1] https://www.theregister.com/2020/11/19/apple_m1_high_bandwid...

kristianp2• 6 years ago

On a related topic, will Apple need to go up to LPDDR5 to get to 32GB of RAM? I read a comment a day or so ago that said that LPDDR4 is limited to 16GB. I'm wondering if Apple can release a 32GB machine within the next 6 months.

cpmsmith• 6 years ago

but at $200/ 8GB, getting up to 32GB or 64GB is going to be a challenge and quite expensive

It's worth noting that Apple's price for the upgrade doesn't necessarily tell us much about the actual cost to them. They've famously charged exorbitant amounts for RAM for a long time, including charging that same rate, $400/16GB, to bump up the RAM on the current (Intel) 16" Macbook Pro:

https://www.apple.com/shop/buy-mac/macbook-pro/16-inch-space...

ogre_codes14• 6 years ago

Yes!

I updated my comment hopefully made it more clear. The issue is less about the $$ amount, and more about the practicality of including ever larger amounts of RAM on the SoC.

kllrnohj17• 6 years ago

Moving high bandwidth RAM to be shared between the CPU & GPU

There's a really weird amount of focus on this. Unified memory has been a thing for almost half a decade now. It become a thing as soon as AMD stuck the CPU & GPU behind the same IOMMU ( https://en.wikipedia.org/wiki/Heterogeneous_System_Architect... )

Now you may ask, but why hasn't anyone leverage this before? And the answer is they have, but it's usually not worth doing because usually the integrated GPU isn't worth using for anything. As in, the market for HPC software that doesn't benefit from a discreet GPU is vanishingly small. So nobody really cares about it. But there are applications of this. Things like Intel's QuickSync should be internally leveraging this on the relevant CPUs, for example. So those sorts of frameworks (like MLKit) will just be a bit faster and cheaper to spin up.

The rise in consumer software that does "HPC-like" workloads (eg, facial recognition, voice recognition, etc..) make this more interesting, but there's nothing new here, either. It's certainly not playing any meaningful role in the M1's current performance. The bigger question here would be to what extent does Apple push this. Like is Apple going to try and push integrated GPUs for the iMac Pro? What about the Mac Pro?

tjalfi2• 6 years ago

Unified memory is quite a bit older than that; the SGI O2[0] had it in 1996.

[0] https://en.wikipedia.org/wiki/SGI_O2

ogre_codes14• 6 years ago

There's a really weird amount of focus on this.

Considering how much emphasis Apple put on it, I don't think it is weird at all. Apple made big claims about their CPU and attributed a significant chunk of that performance gain to their unified memory.

Their claims about the CPU have proved largely accurate. Why would they fabricate the reasons behind that performance? It's not like they are throwing off competitors here.

vvanders• 6 years ago

The whole focus on this makes no sense to me as well. UMA has been standard architecture for mobile SoCs since the dawn of time(aside from a few oddballs). Ditto tiling GPUs and the few other things I've seen called out.

Heck the XBox 360 used UMA[1] and the PS3 didn't[2]. It really didn't play into the systems performance directly(other than you might do some crazy tricks like store audio data in VRAM and stream it back). With UMA you can get into cases where heavy CPU reads can impact other parts of the system because the memory controller is shared.

[1] https://en.wikipedia.org/wiki/Xbox_360_technical_specificati...

[2] https://en.wikipedia.org/wiki/PlayStation_3_technical_specif...

mywittyname• 6 years ago

with perhaps 32GB of onboard memory and the external RAM being used as swap?

I wouldn't be surprised if Apple was working on some ways to optimize swap so that SSDs can fill the roll of "external ram." At this point, PCI Express has the theoretical bandwidth to compete with DDR5, but it can't handle anywhere near the number to transactions. But I bet with some clever OS-level tricks, they could give performance that's good enough for most background applications.

lodovic• 6 years ago

You could take a stack of DIMMS, add a memory controller and a USB-C interface, and create the world fastest external swap drive.

wtallis5• 6 years ago

Apple's still working with the same NAND flash memory as everyone else, so there's little opportunity for them to do anything particularly clever at the low level.

But even looking at commodity hardware, high-end SSDs are already capable of handling a comparable number 4kB random reads per second to the number of context switches/page faults a CPU core can handle in the same second. The huge latency disparity is the problem: the SSD would prefer you request 4kB pages dozens at a time, but a software thread can only fault on one page access at a time. Using a larger page size than 4kB will get you much better throughput out of a SSD. On the OS side, swapping out a large number of pages when the active application changes can make good use of SSD bandwidth, but when a single application starts spilling into swap space, you're still fundamentally screwed on the performance front.

masklinn3• 6 years ago

They moved high bandwidth RAM to be shared between the CPU & GPU, but they[1] can't just keep expanding the SoC with ever larger amounts of RAM Perhaps they will have external RAM in addition to the on chip RAM, with perhaps 32GB of onboard memory and the external RAM being used as swap? This takes a bit away from the super-efficient design they have currently.

The RAM isn't on the SOC, it's soldered on the package, which is a very different proposition. Possibly so they don't have to bother routing on the board (meaning they can shrink the board further), and can cool the RAM at the same time as the SoC (without the need for a wider cooler base).

The PS5 also has unified memory and uses faster RAM, the RAM chips are soldered on the board around the SoC.

ogre_codes14• 6 years ago

The PS5 also has unified memory and uses faster RAM, the RAM chips are soldered on the board around the SoC.

Perhaps this won't be as limiting as I suspected.

dev_tty018• 6 years ago

To your main points, they have yet to fully utilize advanced packaging (TSMC 3D for example) to get much more RAM in the SOC. They could also go off package at the expense of power, a good tradeoff for a desktop system. The die size is also small compared to competitive processors (120 mm^2) so they can certainly add more cores. I think with a larger cost budget they'll make the high end sing.

I don't mean to pick on you as you're not alone in what is a very natural skepticism. However, it is somewhat amusing to watch the comments about the M1 over time. When Apple announced the M1 based products many critics were crying impossible, faked, rigged benchmarks, etc... Now that the products have proven to have performance at least as good as claimed, lots of people are suggesting this is some kind of low end fluke result and the higher end systems won't be so great. Just wait. I think we are seeing a tipping point event where RISC (fueled by great engineering) is finally fulfilling its promise from many years ago.

ogre_codes14• 6 years ago

To your main points, they have yet to fully utilize advanced packaging (TSMC 3D for example) to get much more RAM in the SOC.

The big problem is as you get larger and larger amounts of RAM, the demand drops precariously. The number of people who need 16GB of RAM? Very large. The number who need 32GB is at least an order of magnitude smaller. The number who need 64GB another order of magnitude smaller. The number who need 256GB of RAM or more is likely in the low thousands or even hundreds.

Making a custom package for those kind of numbers becomes prohibitively expensive.

I don't mean to pick on you as you're not alone in what is a very natural skepticism. However, it is somewhat amusing to watch the comments about the M1 over time. When Apple announced the M1 based products many critics were crying impossible, faked, rigged benchmarks, etc

I've figured from the start that Apple wouldn't make this transition unless there were a significant win here. In my above comment, I think I made it quite clear that I expect Apple's upcoming CPUs to outperform Intel.

I'm just not as certain the delta between Apple's top end CPUs and Intel/ AMD will be as great as the delta between the M1 and the Intel CPU it replaced. So for example, the M series chip might be 20-30% faster than the Intel in the 16" MacBook Pro, not double the performance as it was in the MacBook Air.

socialdemocrat6• 6 years ago

Interesting, where do you find the size of these dies? I was really curious about how large the Firestorm cores are compared to say Zen3 or Intel cores.

How many cores do you think Apple can realistically add? Can they get up to something like threadpiper. or are we talking more about something along the lines of a 12 core upper limit?

kllrnohj17• 6 years ago

To your main points, they have yet to fully utilize advanced packaging (TSMC 3D for example) to get much more RAM in the SOC.

The M1 is using off the shelf LPDDR4 modules on the package but not on the die. 3D stacking is possible for denser DRAM modules but wouldn't make much sense compared to just adding 2 more DRAM modules and spending the physical space on it - there's more than enough room especially in devices like the Mac Mini. A boring ol' daisy chain setup would work perfectly fine here.

socialdemocrat6• 6 years ago

This is something I have been trying to understand. What is the practical limit today? How many cores, and how much more memory can Apple add before they run out of Silicon? From what I understand there are a number of practical limits to how big they can make the silicon die, because the equipment on the factories are not really made for arbitrary large chips, and anyway the defect rate will quickly rise if you make too large chips.

Like can we expect say something like a 32 core M3 chip with 64 GB RAM, or will that be too much for this design?

freehunter• 6 years ago

I'm kind of wondering how scalable the performance increases they made here are

It's a good question and really only time will tell, but this same comment was made about these chips in the iPhone: "impressive yes, but would they be able to scale up to power a laptop?" A lot of people said no back then, and yet here we are.

Apple's not stupid and they're not going to slap Intel in the face like this if they're not 100% sure they won't need them again in the future. I'd be willing to bet they already know the answer to these questions (and likely even have 32/64GB M1s running in their labs). There's just no way they'd go into something like this blindly.

hollerith• 6 years ago

Apple's not stupid and they're not going to slap Intel in the face like this if they're not 100% sure they won't need them again in the future.

Is there some explanation why AMD processors are unsuitable in, e.g., the Mac Pro?

ogre_codes14• 6 years ago

I thought I was pretty clear that I fully expect Apple will be able to migrate their entire line.

My only question is whether they will blow the doors off Intel/ AMD the way they did with the M1. With the MacBook Air (and largely with the base MacBook Pro), Apple was able to more than double the processor speed even while increasing processor speed. I'm not convinced we'll see that kind of explosive speed improvements with the 16" MacBook Pro. Battery life will almost certainly trash the current MBP. I'm just not confident we'll see the base 16" MacBook doubling its CPU performance.

FWIW, I don't see anything Apple has done as a slap in the face. They've been pretty reasonable about not mentioning Intel in their performance numbers. Instead all metrics are based on the performance of previous generation MacBook Air.

ksec2• 6 years ago

Just to add a few things.

The HBM confusion comes from Apple Marketing, they have since corrected the phase.

It uses LPDDR4x, fairly standard across the industry.

The LPDDR4 spec allows up to 8 Channel per package ( Although I have not yet seen any manufactures announced such a SKUs ), meaning Apple could scale to 32 GB, or with LPDDR5 using the same setup gives them 64GB while increasing the bandwidth by ~30%+.

From a portable perspective I think 64GB is good enough. Not to mention larger size of RAM being unsuitable for product with battery.

I have no idea how their Desktop part will play out, especially when Memory bandwidth is required for their universal memory.

d33lio• 6 years ago

It'll be curious when they inevitably release the "M2" chip with higher memory capacity. If M2 has 32gb support I'll buy one immediately. For now, I'll be sticking to my "never buy gen 1 of any technology" rule. Right along side my, "use tech until it breaks" rule, however if you incentivize yourself to be a "power user" meeting the latter rule is far easier than the former ;) .

stetrain• 6 years ago

You can see the gaps in the lineup that they have yet to fill, since the 4-port 13" Macbook Pro and high end Mac Mini are still being sold with Intel CPUs.

Both of those machines need at least 32GB options to properly replace them. I would guess we see that support in an M1X with more cores and more Thunderbolt lanes next year as they work their way up the lineup.

grecy2• 6 years ago

It's a total guess, but I figure "M" is for "Mobile", and it will increment up in numbers like the A series has done in iphones/ipads

Then we'll see some other letter (Maybe) "D1" for Desktop perhaps for the machines next up the list performance-wise (higher-end Mac Book Pros and minis and lower-end iMacs.)

And finally we'll see "P1" for the pros, which is the iMac Pro and Mac Pro. The real beast, hoping for at least 128 cores.

All of them will just go up in number as the years go on.

MBCook• 6 years ago

never buy gen 1 of any technology

I totally understand that sentiment, but in some ways this isn’t the first generation. While it’s the first desktop chip that Apple has RELEASED, they’ve been making their own chips since the iPhone 5s (IIRC). I imagine all the big bugs are sorted out.

qz22• 6 years ago

This. So far, after a week, my M1 is flawless. This is not first gen tech by a mile.

I’m slightly in shock to be honest. I was about to bail out to Linux and buy a monster PC but I can’t get a new Ryzen or Radeon card at the moment due to supply so I blew the cash on a Mini, which was actually in stock.

faitswulff4• 6 years ago

By the time docker, virtualization, and programming environments are mostly sorted out, there will likely be a successor to the M1 on the market, so while I'm not GP, I do agree with the sentiment in this case. Especially with an ISA change.

lend000• 6 years ago

I'll be waiting for the M3X in 2022, at which point they should be using TSMC's 3nm node (another 15% more performance and density) and have had 2 years for the software ecosystem to get settled on ARM.

_ph_4• 6 years ago

I think if you want a MB Air, it is absolutely fine to by now, as the M1 has precisely targetted for this machine. For the other machines, for sure there are variations to come which have more cores, more memory etc. For those, you should wait until they appear.

wil4213• 6 years ago

Buying an M1 now that I will give to my wife once the M2 16 inch comes out. A family member opted for an iPad over a 15 inch MBP that was collecting dust so I’m not really out any money on the tech until it breaks rule.

I almost ordered an intel 16 MBP inch a couple weeks ago. Thankfully I didn’t pull the trigger.

AnthonyMouse2• 6 years ago

The explanation provided by the article is poor. It has very little to do with SoC or specialized instructions -- it's fast on general purpose code.

The main reasons appear to be that it's a solid design, i.e. competitive with what x86-64 processors are offering, and on top of that has some specific characteristics that x86-64 processors don't currently have (but obviously could). It's built on TSMC 5nm, which is possibly the most power efficient process in the world right now. It's using memory which is faster than the DDR4 currently used by the competition. It's a big.LITTLE design, which is more power efficient, because you get strong single thread performance from the big cores and higher efficiency on threaded code from the little cores.

It's not magic. It's engineering.

westwing• 6 years ago

The article goes into what makes it fast on general purpose code in the bottom half. Mainly, it's the better out-of-order execution that is possible with a large ROB, and how this wouldn't work as well on X86.

Your points don't explain why at 3Ghz this chip can outperform 5Ghz chips in single-threaded workloads. Using a 5nm process can give you more cores and less power usage, but it won't improve IPC. The DDR4 is faster than average, but you can get those kinds of speeds on enthusiast PCs and it doesn't make a big difference there.

AnthonyMouse2• 6 years ago

Your points don't explain why at 3Ghz this chip can outperform 5Ghz chips in single-threaded workloads.

It's a trade off. Making it wider is the reason the IPC is higher, but it's also the reason it is a 3GHz chip instead of a 5GHz chip.

The author's explanation of why x86 processors can't do this is also not especially compelling. The reason very wide processors are atypical is that common spaghetti code has poor instruction level parallelism -- the processor can't extract what isn't there, so there is a point at which higher clocks become the way to make bad code run faster. Interestingly, synthetic benchmarks are often less susceptible to this because the code is optimized to maximize ILP. It's a shame we still have so few real world benchmarks (mostly because the applications still haven't been ported).

The DDR4 is faster than average, but you can get those kinds of speeds on enthusiast PCs and it doesn't make a big difference there.

It depends heavily on the task, but the difference in some cases is close to 40%:

https://www.tomshardware.com/reviews/best-ram-speed,5951-6.h...

ahupp2• 6 years ago

But Apple has a crazy 8 decoders. Not only that but the ROB is something like 3x larger. You can basically hold 3x as many instructions. No other mainstream chip maker has that many decoders in their CPUs.

Does this mean I'd expect to see better IPC (instructions per cycle) on these chips vs an x86, due to better memory parallelism?

jonplackett8• 6 years ago

Yes that's that main reason the article gives that a 2.3ghz laptop chip is almost as fast as a 5ghz zen3 chip with a lot more cooling.

areoform2• 6 years ago

As I've written elsewhere and the article discusses in excellent detail, something that's missing in the conversation is a discussion of the custom application specific silicon over here, https://areoform.wordpress.com/2020/11/30/tanstaafl-apples-m... (on HN, https://news.ycombinator.com/item?id=25256025 )

I dislike linking to myself, but the take is long and it essentially points out that Apple themselves hint at Application Specific silicon in the M1 in their keynote, and when added with their acquisitions of ASIC specialists, it's not a long-take to say that comparing the M1 against most vanilla X86 processors isn't quite fair. It's a very different beast with its own tradeoffs.

By colocating several different application specific processors under one roof and selling it as a CPU, Apple may have revitalized/invented something new. It's a bit like the iPhone - taking elements that were already there and catalyzing them into a new form. This new not-quite-a-CPU SoC likely has significant implications for the future of computing that should be discussed and detailed. Because,

There Ain't No Such Thing As A Free Lunch.

pram• 6 years ago

A lot of the stuff you’re referring to as “application specific” is already present in Intel Macs with the T2 chip. Except obviously slower and older. People aren’t discussing it because it isn’t really “new”

areoform2• 6 years ago

They have indeed moved the system controller etc from the T2 onto the M1 more or less wholesale. If you look at the TEM image I have added to my post of the M1's sister chip, the A14, you'll see that the classical CPU and GPU take up only a small fraction of the die. The rest isn't memory as a naive take would suggest. It's custom silicon handling a large basket of previously CPU tasks.

_2d30• 6 years ago

But the cores are really good in real world, general purpose computing so I'm not sure the ASS (Application Specific Silicon) is more than half the story.

mrkstu2• 6 years ago

No more a tradeoff than something like AVX-512 though right? Or the custom instructions Intel will add for large customers like Facebook?

rsynnott• 6 years ago

While that’s no doubt helping in, say, classifying photos in iPhoto, it’ll do nothing for SPECInt. The impressive general purpose benchmark results are down to the CPU.

kodisha• 6 years ago

It's almost 2021.

Is it still ok to post paywalled articles?

seek3r2• 6 years ago

It’s almost 2021.

Is it still ok to post Medium articles?

rat9988• 6 years ago

We are better with paywalled articles than without. Moreover, writing articles doesn't necessarily have to be free work.

jonnycomputer4• 6 years ago

So my 2012 MBP is on its last legs (love that thing). So now we have the M1, and I'm hearing impressive things. But my question is, as a developer who does, lets face it, pretty much the gamut, will I be handicapped in the near term? I use a combination of IntelliJ IDEs and Emacs, with MacPorts, and a large variety of open source and closed source tools. I just don't want the headache of having some part of my workflow cutoff.

jonplackett8• 6 years ago

In almost the same position (MacBook Pro 2013) and I plan on waiting for the 16". By the time that's out we'll see how many of these things are getting quickly ported - my expectation looking at how excited every is, is that things will get ported FAST. But there's time to wait and see before the one I actually want comes out.

PeterisP2• 6 years ago

Well, at least Homebrew are claiming that "There won’t be any support for native ARM Homebrew installations for months to come." (https://github.com/Homebrew/brew/issues/7857) so if you rely on a large variety of open source and closed source tools that might be a problem.

vimy• 6 years ago

Almost everything works if you start terminal in rosetta mode. cmd+i on terminal.app and check the rosetta box.

TuringNYC• 6 years ago

Same question here, except I disagree with all the discussion on other threads about "wow, 16gb RAM is magically sufficient for most use cases." I'm sure it is now sufficient for web browsing + IDE + Slack, but what about anything beyond that?

I realize 16gb RAM goes farther on M1 vs before, but some things just need RAM and there is no way around it. If i'm running a VM or multiple VMs (e.g., for android app development), or multiple docker containers -- I just need more RAM.

I'm hoping that the upcoming 16" MBP upgrade offers more RAM tiers.

saagarjha9• 6 years ago

MacPort isn't doing all that badly right now.

jonnycomputer4• 6 years ago

is this based on your own experience?

greyhair8• 6 years ago

Just had this discussion at work. We have a mix of MacBook Pros and high end Windows 10 laptops, and every one of them is running a VM hosting Ubuntu 18.04

Is the M1 going to have a VM capable of running a native Ubuntu instance?

thoughtsimple5• 6 years ago

MacPorts is working pretty well. About 80% in my testing. I've been able to work around anything that doesn't build. It seems much further along than HomeBrew.

jonnycomputer4• 6 years ago

Good to hear (for us MacPorts users!)

jonnycomputer4• 6 years ago

Based on what people are saying here, it does seem that by the time the 16" comes out, support should be pretty good. That's pretty impressive, in a way.

mjg59• 6 years ago

Intel will already sell you a CPU/GPU with a unified memory architecture and hardware video encode/decode. Intel's mobile parts are already SoCs (the U and Y models have the PCH on-chip, and the U's TDP range is probably the closest to the M1). These are not the reasons the M1 is faster than x86, but the article focusing on them so much means I'm more skeptical about the claims around OOP.

SoSoRoCoCo• 6 years ago

A few years ago, Apple's Portland, Oregon office hired dozens of top architects away from the Intel site 10 miles away (for big $$$). For those of you that don't know Oregon Hosts D1X (Intel's gigantic cutting-edge fab) and several architecture teams, predominantly veterans from the P4 product line.

This probably has something to do with it.

tigen• 6 years ago

"Now you got a big problem, because neither Intel, AMD or Nvidia are going to license their intellectual property to Dell or HP for them to make an SoC for their machines."

This isn't quite correct. AMD and Nvidia have made custom SOCs for game consoles for years now; they could create customized SOCs for PCs if this was a critical issue. But I don't believe it is. The PC workloads and use cases follow well-known patterns and market segments and you don't really need a lot of different custom accelerators, or be on a single SOC for that matter. Video-related processing has been part of GPUs for many years.

For that matter, making RISC CPUs is not actually a huge obstacle for these guys. (Nvidia does.) Yes even Intel.

The article also seems to entirely omit the M1's heterogenous core strategy, where 4 of the cores are high performance and the other 4 are optimized for power efficiency. A deeper analysis of this and how software manages them would be more interesting.

Tsarbomb• 6 years ago

Not to mention, that AMD's IO / Memory controller has a whole ARM CPU on the same die for handling their platform security.

spideymans• 6 years ago

The article also seems to entirely omit the M1's heterogenous core strategy, where 4 of the cores are high performance and the other 4 are optimized for power efficiency. A deeper analysis of this and how software manages them would be more interesting.

When the CPU utilization ramps up on M1 MacBooks, the user interface always remains buttery smooth. I haven't been able to make the M1 Air drop a frame yet no matter how hard I push it. Meanwhile doing anything remotely CPU intensive on an Intel MacBook will turn the user interface into a janky stuttery mess.

I suspect the heterogeneous cores are the "secret" behind this. Performance tasks are delegated to the performance cores, leaving the efficiency cores free to instantly respond to any UI-bound tasks.

rhencke• 6 years ago

https://en.wikipedia.org/wiki/ARM_big.LITTLE might yield clues

wil4213• 6 years ago

Where do you have frame drop issues on your intel Mac? I have a 2017 15 inch with the best i7 and run a 4K and 1440p monitor with no noticeable issues. Just ordered an M1 Air.

fomine36• 6 years ago

AMD does but AFAIK Nvidia don't license modifiable IP for Switch, PS3, Original Xbox.

tommoor• 6 years ago

I found this recent ColdFusion video on the background of ARM and RISC processors really educational, I think most will learn _something_ from it: https://www.youtube.com/watch?v=OuF9weSkS68

littlecranky67• 6 years ago

I am wondering how the M1 is doing regarding the various side-channel attacks that came to live with the Spectre/Meltdown publications. Is the M1 less prone to side channel attacks by design, or is this just something not yet known?

dylan604• 6 years ago

I'm sure it'll be impervious to any attack vector just like the T2 chip. Oh, wait. Ooops.

I'm sure all of the hackers are having a field day looking for vulns in the new chip. It'd be a hacker's fantasy to be the first one to find something on the brand new chip.

saagarjha9• 6 years ago

The core design is largely identical to the Apple's mobile processor line.

dreamcompiler2• 6 years ago

As the article points out part of the reason is that the ARM's RISC instruction set has a lot more room for optimization than the x86 CISC instruction set, which Intel has been milking since 1972. If that were the whole story, ARMs would have been faster than Intel long before now, so there's obviously much more going on than simply RISC vs. CISC.

Still, I find it gratifying that my least favorite instruction set of all time may finally be going the way of the dinosaur.

AsyncAwait• 6 years ago

Still, I find it gratifying that my least favorite instruction set of all time may finally be going the way of the dinosaur.

Only I fear it won't be replaced by anything more open.

KingMachiavelli• 6 years ago

Vertical integration seems to have really paid off for Apple as it's really what allowed them to pull this off. While I certainly expect cloud providers to continue adopting ARM CPUs, I'm worried that the enthusiast/DIY desktop market will be irrelevant if x86 continues to lag behind ARM. It certainty doesn't seem like buying an Ampere server is as simple as getting an x86 machine. Perhaps POWER10 or eventually RISC-V offerings will become more accessible & competitive?

mhh__2• 6 years ago

Power 10 does have some nice features so it would be pretty nice to see IBM seize the opportunity, not that they will.

faitswulff4• 6 years ago

Regarding vertical integration, I wonder if their owning the OS and the hardware stacks lead to special insights on what would lead to better performance.

_ph_4• 6 years ago

And they are completely unconstrained in where to put the compute. They can decide to add new special hardware to the SOC and just support it in the OS.

raverbashing2• 6 years ago

It's an interesting take, and I agree with the issue being the x86 difficulties. There was a link today about "how many registers an x86 processor has" and it really reminded me of how many issues and legacy the processors have to deal with

I think the solution would be to move the x86 cruft to an SW emulation layer, and focus on base performance. Something like this (though I'm skeptical of taking things like rings and memory protection out of hw http://www.emulators.com/docs/nx03_10fixes.htm )

Your latest Intel chip boots like an 8086 from the 70s and it has to do several steps before it goes to protected mode. It has to deal with x87, MMX, SSE, SSE2, AVX etc (ARM has NEON and that's it.). Every register has several ways of being accessed: AH/AL, AX, EAX, RAX. Wanna access a partial part of a register on ARM? AND/Shift.

mhh__2• 6 years ago

X86's legacy really only affects the decoding logic, whereas the actual CPU itself could be almost any superscalar execution stage (simplified).

For example, amd64 has about 20 general purpose registers, but the silicon that actually executes it could have something like an order of magnitude more to play with (i.e. for register renaming)

raverbashing2• 6 years ago

From the article

If we have more decoders we can chop up more instructions in parallel and thus fill up the ROB faster.
And this is where we see the huge differences. The biggest baddest Intel and AMD microprocessor cores have 4 decoders, which means they can decode 4 instructions in parallel spitting out micro-ops. But Apple has a crazy 8 decoders. Not only that but the ROB is something like 3x larger. You can basically hold 3x as many instructions. No other mainstream chip maker has that many decoders in their CPUs.
You see, for x86 an instruction can be anywhere from 1–15 bytes long. On a RISC chip instructions are fixed size. Why is that relevant in this case?
Because splitting up a stream of bytes into instructions to feed into 8 different decoders in parallel becomes trivial if every instruction has the same length.

tehjoker2• 6 years ago

So in the (excellent) article, they have two advantages: System on a Chip and enhanced out of order execution. Wasn't out of order execution implicated in Spectre and Meltdown? How are they mitigating this issue? I imagine for a new chip they could design something in.

annilt3• 6 years ago

Out of order execution makes your code run faster like 20x-50x. You can’t produce a CPU without it and compete in the market. There are many variations of spectre and meltdown bugs, some of them might be fixed in the CPU and some in the OS. So, there is no simple answer to your question I believe.

tehjoker2• 6 years ago

I would just wonder if increasing the quantity of OoO makes mitigation more difficult in some way.

wiremine• 6 years ago

I keep coming back to the implications for the rest of the industry:

1. What does this mean for x86?

2. What does the answer to question #1 mean for Windows and Microsoft? Are they going to sit by and let Apple lap them?

3. What does the answer to question #2 mean for cloud computing? AWS is already making ARM chips... does the M1 change anything fundamentally about where the cloud goes with ARM?

gtirloni• 6 years ago

At least for #2, see Windows ARM

https://docs.microsoft.com/en-us/windows/arm/

pishpash• 6 years ago

#1: The writing's on the wall for x86, probably. Once its former monopoly rent is only justified by high-end "scientific computing" uses -- well you know what happened to IBM/DEC/SGI/HP and their workstation solutions...

__d• 6 years ago

1. x86 (and then AMD64) has had vast amounts of R&D money and talent thrown at it for decades, with the result that it has out-performed every competitor: SPARC, MIPS, Alpha, PA-RISC, Itanium, etc. As a consequence of this domination, it has a massive software, tooling, and expertise advantage.

But ... ARM, which through a series of coincidences, ended up being the right architecture at the right time for mobile devices, has had its own injection of talent and money, and has advanced rapidly in the last 15 years. The M1 is a long way from the ARM710 or StrongARM of the late 90's!

Similarly, computer circuitry has evolved. Early minicomputers used small circuit boards with just a few gates to assemble their CPUs. In the early 80's, bigger CPUs were built from multiple "bit slice" chips ganged together. The modern PC motherboard has been a thing since the era of the Apple ][, growing through 8, 16, 32 and now 64 CPUs with ever-increasing speed and power, but maintaining a model of a motherboard and expansion cards. SoCs have been a thing for embedded devices for some time now: the M1 is perhaps the first really high-profile "computer" to use this technique to integrate its major architectural components in one "chip" (package). I think it's inevitable that others will follow, given the obvious performance and power gains to be had.

AMD and Intel do this to some extend already. The AMD chips powering the new Platstation and Xbox consoles are SoCs, and Intel has sold embedded variants of its CPUs that are basically SoCs for some years now too.

x86 has a long future ahead of it, but for the first time since Alpha (?) it's seeing a major competitor. Unlike DEC though, ARM has a broad and deep ecosystem behind it, and (as the article points out) there are some advantages to the instruction set that x86-64 will perhaps struggle to overcome.

2. Microsoft already has the Surface. They've known for some time that Apple's integration of hardware and software is hard to beat, and that the iPhone represented a technology that could be applied to laptops and desktops any time Apple wanted to do so. So ... they've already made steps in the direction of competing, but they have a lot of business-model challenges to overcome in order to do so.

Honestly, I'd be much more interested in the futures of Dell, HP(E), Lenovo, etc, than Microsoft. This is a massive challenge for them.

3. No. The cloud vendors are already moving towards ARM for power reasons. The AWS Nitro board is begging to be integrated with a Gravitron -- I would be surprised if Amazon doesn't come up with a compute platform that's powered by a similarly integrated SoC in the very near future.

The M1 helps accelerate this process because all Open Source software will now have to treat AARCH64 as a first-class citizen (which, to be fair, the Raspberry Pi has already helped to do). Similarly, commercial software vendors now have another market that will need a native ARM version in 2 years (after Rosetta2 is phased out, like Rosetta was for PPC). So .. I don't think it's changed the cloud direction at all, but it could make the transition faster.

kristianp2• 6 years ago

Intel is going to be strongly motivated to pull their finger out and match the performance of the M1. Increase the performance of the chip, and release SOCs with RAM on the package for laptops, not just for phones.

gameswithgo4• 6 years ago

There are some technical things I feel are somewhat misrepresented:

1. Why don't AMD/Intel use a unified GPU/CPU memory setup like Apple? Because the big discrete gpus would be too big and hot to be part of the same chip as a cpu, and need faster memory than DDR4.

2. Zen3 is clocked at 5ghz: the best of them can turbo to 4.9 for a little bit, base clocks are ~3.4 to 3.8 depending on core count / model

socialdemocrat6• 6 years ago

There has been talk of using eGPUs with the M1 chips. Obviously there would be downside to having to move stuff over a slow Thunderbolt 3 connection but given that the GPU can be much bigger, how do you think that would play out?

Would that offer higher performance? If so on what kind of workloads?

baybal27• 6 years ago

Why don't AMD/Intel use a unified GPU/CPU memory setup like Apple?

Well, they do, for like 10+ years now

avmich• 6 years ago

Requires an account. Is there a less restricted URL for the story?

npiit• 6 years ago

Apple M1 is so fast because you paid a lot for it and want to feel good about that I guess.

spamizbad2• 6 years ago

Gotta say I'm not a fan of this article. A few points I really disagree with:

1) It puts way too much emphasis on the ISA being a driver for performance. People have been making this claim against x86 forever, going back to the 90s when RISC chips started putting up some very impressive performance numbers. Lots of talk about how the x86 ISA was out of runway. This period existed fo a grand total of about 4 years (94 thru 97) until the Pentium II hit the market, which allowed PCs to start cutting into the workstation market. AMD creating the x86-64 extension handled the addressing limitation well too, letting it flourish in the server space as well.

2) The author seems to think Intel or AMD cannot make SoCs because of their business model. This really isn't the case, and both companies have slowly been moving more "stuff" on package. AMD is already there with the xbox an playstation chips they manufacture. AMD's chiplet approach would be particularly adroit at exploiting this. I get the feeling both AMD and Intel would LOVE it if PC vendors started demanding SoCs. And while the M1 has lots of little speciality processors onboard, both AMD and Intel have more robust processor I/O. That's by design: The M1 isn't designed for the person who needs a gazillion PCI-E lanes for storage and networking (the M1 is likely has half the PCI-E lanes as consumer Zen2/3 cpus and 1/4th to 1/8th compared to Threadripper and EPYC)

3) Glosses over the fact that one of the greatest challenges in computer architecture is coping with the so-called "memory wall": there's a growing latency chasm between cache and memory. Apple cleverly mitigates this by using very fast, low latency memory (LPDDR4x 4266 MT/s vs DDR4 at 3200 MT/s in x86 CPUs). But beyond how many MT/s you're operating with, I would love to see some latency figures. They likely blow your typical consumer DIMMs out of the water. Both AMD and Intel wok around this limitation with larger caches and smarter prefetching, but that only gets you so far. edit: And I would wager much of its impressive performance figures comes from Apple's approach to addressing the memory wall. Memory latency benchmarks seem to strongly favor the M1 over both AMD and Intel CPUs.

pclmulqdq5• 6 years ago

The Intel ISA has some very powerful instructions that allow it to keep performance up, but unfortunately decoding n x86 instructions involves doing a number of things that are O(n) in latency and O(n^2) in chip area/power - both instruction boundary detection and micro-op scheduling (since instructions can emit more than one uop) are included here. This isn't too bad when n is 4, but it has stressed both AMD and Intel's capabilities to make it to 8, and I don't think anyone would ever seriously consider building a 16-wide x86 machine. Once memory and I/O buses get fast enough to feed a 16-wide general-purpose computer, x86 as an architecture is in trouble. They have quietly gotten fast enough to feed an 8-wide machine.

LPDDR4 very quietly took the speed crown from DDR4 due to the fact that the signal integrity problems are less demanding (soldered vs DIMM being the standard interface), and it looks like the DDR interface may be near the end of its useful life. Transceiver-based memory modules using standards like CXL and CCIX may be the long-term fix to the problems of DDR4. In the short-term, those are going to hurt, but long-term they should be a lot better.

gpderetta5• 6 years ago

Common knowledge is that going wider quickly hits diminishing returns so generally there hasn't been a lot of pressure for x86 to go wider.

It seems to be working for Apple though possibly because they are targeting differen trade offs (lower clock speed for example); but maybe their secret is a better modelling of common workloads revealing this common knowledge to be outdated.

OldHand20182• 6 years ago

The author seems to think Intel or AMD cannot make SoCs because of their business model.

You gave a good example of AMD, but Intel has been making the Xeon-D SoC for a while now. They've always looked interesting to me, but outside of expensive SuperMicro motherboards, I've never seen one available to the general public.

I think you are right though - both AMD and Intel would love it if vendors demanded high-performance SoCs.

https://en.wikipedia.org/wiki/Xeon_D

toast0• 6 years ago

fwiw, I think Intel declared the Xeon-D line dead. They're not planning anything new there.

That said, I don't think they would need much to make a Core series processor into a SoC; the chip does almost everything you'd need already; memory, some of the pci-e, (some) usb, (some) sata, legacy IO are already in the CPU for both Intel and AMD, and both offer chips with GPUs on board too. AMD has a 'chipless' chipset available for ryzen, the A300, it even has a new performance version, the X300. There's still plenty of other chips on the board, but there's nothing that's really a chipset.

klelatti4• 6 years ago

On 1) I think that you're right about the impact of the ISA being overdone but lets not forget that Intel has had a process advantage for a long time and that it was partly the volume of consumer sales that supported their R&D and helped them win on servers. That situation has changed now - the process advantage has gone and there is lots of money pouring into TSMC and the mobile SoC designers.

For me the key point on the ISA is that Arm is not limited to two companies: what we've seen in other markets will happen in desktops and servers - the really big customers can take the ISA and build highly competitive SoCs that suit them on the leading process technology and for lower cost.

jsmith45• 6 years ago

By what measure are modern AMD CPUs not an SOC (especially the APU models)? They literally can function without a chipset.

The chipsets are little more a PCI-E extender with some built in USB and SATA controllers connected to it.

The CPUs do perform some form of handshaking with the chipset, but after that is done, it does not care. This handshake is literally about being able to lock out certain on die features if you don't buy the more expensive chipsets. (Or partner with AMD to get access to an small 8 pin activator chip to unlock the features you need, and add your own PCI-E extender if desired).

spamizbad2• 6 years ago

I agree but I think the author is using a different standard and I’m saying AMD and Intel already meet that standard.

pkulak2• 6 years ago

All these specialized co-processors make me a bit sad. I've already got a graphics card that can decode some video formats, but not new ones, and that will never change until it becomes e-waste. Now we get the same thing for image formats, ML, etc? And you're even more locked in to these co-processors since they use space that could have been used to have a dozen general purpose cores. So good luck ever watching a video that doesn't use a codec your hardware supports.

amelius3• 6 years ago

I'd be ok with coprocessors if there was an easy way to swap them in and out.

greyhair8• 6 years ago

A lot of modern hardware coprocessors are hybrid blocks that can be configured through firmware. You can dedicate a very small DSP with the block to feed and manage it. I haven't been involved in a new chip design in a few years, but a lot of specialized cores were vector processors (very narrowly defined vector processors). I don't know if that has changed.

I find it surprising that you have a graphics card that won't decode new video formats, unless the vendor has completely abandoned support for it. I have never encountered a modern graphics card that wasn't completely configured and run with firmware.

pkulak2• 6 years ago

Maybe I just don't pay attention, but I've never heard of new firmware going out to multi-year old graphics cards and adding new features. Sure it may be possible, but what company is going to go through the trouble of that?

randerson• 6 years ago

A lot fewer molecules of e-waste with the tiny SoC, at least.

FullyFunctional2• 6 years ago

I'm am very appreciative to Apple for finally closing the endless "The ISA doesn't matter" nonsense. The ISA does matter and it's part of what enabled Apple to go so wide.

However, there the article is slightly misleading. The ROB isn't where instructions are issued from, that would be the schedulers which usually holds a much smaller set of instruction (16 per scheduler is common). The ROB holds everything that was decoded and not yet retired, thus including instruction that haven't yet been issued to schedulers and more importantly, instruction that have been executed for not retired (eg. might be waiting on older instruction to retire first).

saagarjha9• 6 years ago

Historically, I have yet to see a single case where the ISA has mattered. Every ISA will of course take advantage of its unique features, but in general fast chips come from companies with money and talent, not a particular ISA.

ridiculous_fish5• 6 years ago

I think Itanium mattered. Its EPIC instruction set tried to push the scheduling complexity from hardware into the compiler, which proved too difficult. That's part of why it failed.

jhallenworld• 6 years ago

I (as a tech lead in IBM) had a sales visit from P.A. Semi years ago- we needed a CPU for a co-processor board. We didn't use their chip, and I was amazed that Apple bought them soon after. But then consider who was the founder:

https://en.wikipedia.org/wiki/Daniel_W._Dobberpuhl

mbroncano• 6 years ago

Recently passed, RIP

faitswulff4• 6 years ago

Everyone talks about its top scoring benchmarks, which I presume are the Firestorm cores, but I have to wonder what engineering marvels went into the Icestorm cores?

greyhair8• 6 years ago

Interesting article here, but a lot of the stuff laid at Apple's feet here did not begin at Apple. Yes, they implemented it in a high power design, and yes, they did a great job, and it is really performing well, but all of this has been common in cell phone chips available from various vendors for over a decade.

Multiple cores, multiple DSPs, ISPs, GPUs, secure enclaves, encryption engines, high speed serial controllers, ADC/DAC, plus all the stuff to support the cellular modem such as viterbi encoders/decoders. All these little specialized blocks all embedded on the chip, and the DDR soldered directly to the top of it.

This has been a common technique for over a decade. Why isn't your phone as fast as the M1? How long do you think the M1 would run on your cell phone battery? Everything is an engineering trade off.

So Apple basically took the last decade of smart phone architecture, and blew it up with more transistors, to accomplish more processing throughput.

They didn't invent the technique of hybrid multi-core silicon by any stretch of the imagination.

You can go back to the mid 1990s and find single chip 56K dialup modems with a general purpose CPU, a DSP, onboard RAM, onboard NOR FLASH, and a half dozen dedicated modem hardware blocks, all on a single die.

saagarjha9• 6 years ago

My phone is has comparable single-threaded performance with an M1. But it happens to have an A14 chip inside it ;)

wffurr• 6 years ago

Apple is about three years ahead of any other mobile chip maker. Sure, it's the same type of SoC and general architecture, but somehow Apple's CPU and GPU designs are miles ahead of anyone else.

fomine36• 6 years ago

CPU is exceptionally great but I don't think Apple is also leading GPU. I doubt M1's GPU efficiency is mostly came from 5nm process.

superjan• 6 years ago

I wonder, has anyone written about to what extent XCode has been optimized for the M1? With the wide decoder loop unrolling gets a lot more attractive....

Thaxll• 6 years ago

Also isn't Apple has it "easy" designing a chip from scratch with 0 backward compatibility + they manage the HW + SW.

Intel & AMD have to support thousands of different config:

- I can plug my old memory it works

- I can plug my old graphic card it work ( PCI-e )

Apple has 0 constrains about legacy hardware, software ( beside that emulation layer ), so yes it's a great achievments, but it's very different from designing a chip for PC.

saagarjha9• 6 years ago

You put "that emulation layer" in parentheses but it's no trivial feat writing an x86/x86_64 emulator with high enough fidelity to run almost all Mac apps at almost native speeds.

ridiculous_fish5• 6 years ago

Furthermore the M1 has some hardware support for this, via a runtime-toggle to force x86-style total store ordering.

ebg13• 6 years ago

Every discussion thread about M1 has a dozen people saying "Give me a 64GB M2 with more cores and more ports and I'll buy one." But I just want a 15 inch M1 Air. For most people 16GB and 4+4 is more than enough, and it's the larger screen that differentiates the models.

amelius3• 6 years ago

Did Apple patent anything in their chip?

saagarjha9• 6 years ago

Of course they did.

amelius3• 6 years ago

Care to be more specific?

majewsky• 6 years ago

Question for the chip design crowd here: Would it be feasible for Intel/AMD to design a fast ISA from the ground up and add it as a runtime option to their x86_64 chips? Like, on context switch to userland, the kernel puts the chip into whatever ISA is in the respective process's binary. And the syscall instruction and interrupts put the chip back into the kernel ISA. So you would have backwards compatiblity, but new stuff could use the faster ISA. I guess my main question is if there would be enough die space to support two separate instruction decoders.

greyhair8• 6 years ago

The short answer is no. Basically, you are asking them to really have two sets of cores on a single die and switch back and forth.

I think the more realistic point of view is that x86 has likely run its course, and now it is time to move on.

The long answer is look up Transmeta and do some reading. Basically they designed a RISC CPU core with an external microcode engine, that was able to run x86 instructions. It was a valiant effort, but it didn't work as well as hoped.

Here is a fun history read that mentions Transmeta as well as P.A.Semi. P.A.Semi is the core team that designed the A1 (and following Apple cores) after being bought by Apple in 2008. Prior to that, the team had designed the DEC Alpha (awesome processor) and StrongARM cores. Later, they developed PowerPC cores. A team with really deep CPU talent, and in particular, prior ARM ISA experience, when they were acquired in 2008.

Sorry, I forgot the link on the first post....

https://www.linleygroup.com/newsletters/newsletter_detail.ph...

monocasa5• 6 years ago

You say no, but the PowerPC 615 is an example of a core which did that. You just need two instruction decoders (and get to keep one of them off at a time, which is awesome for dark silicon reasons).

ridiculous_fish5• 6 years ago

This is what Intel attempted with Itanium. The hardware implementation was too slow so they pulled it.

More recently is Nvidia's Denver project, which has a private ISA and dynamically translates ARM instructions. It's an open secret they had it working for x86 too, but it was scuttled due to patent threats.

gok• 6 years ago

I suspect they never shipped the x86 version because it wasn't competitive. Nvidia's CPUs couldn't keep up with contemporary Arm Cortex parts (probably a good part of the reason they bought them), let alone Intel and AMD stuff.

vladletter• 6 years ago

Hello! Thanks for the sharing, would have been nice not doing that on Medium, it's not free anymore. But thanks again!

Sparkyte2• 6 years ago

I just had to jump on here to say how wrong the article is on numerous things.

- Ryzen is an APU - No it's an SoC the northbridge and memory controllers are on the CPU. All Ryzen are SoC. - Ryzen also contains the memory controller on circuit.

- CISC vs RISC - While CPUs are fundamentally this nature for x86(CISC) and ARM(RISC) they both carry similar on level instruction sets today a mix of complex and reduced.

Why is Apple's chips better at the moment? Because they actually been throwing money into the RND of the processor. cough intel cough

You actually see the same perf gains on AMD since it can now flex it's muscles. AMD laptops are getting 10+ hour battery life. If we give AMD a few more years the perf will probably escape the M1 since the chiplet design scales better.

ehejsbbejsk• 6 years ago

I think what will make Apple Silicon a success is that they are not going to purposely slow down progress for the sake of sales and marketing. Apple is still an engineering-driven organization, despite their marketing genius. They’re not going to intro filler products here and there to squeeze the market.

declnz• 6 years ago

Interesting article, and call my cynical but wasn't anyone else immediately reminded of the excellent HN post earlier this month [1], and the Apple big-picture play proposed there?

"Those shiny new Apple Silicon macs that Apple just announced, three times faster and 50% more battery life? They won’t run any OS before Big Sur."

[1] https://sneak.berlin/20201112/your-computer-isnt-yours/

cromwellian• 6 years ago

Couldn't Intel and AMD implement a "Rosetta2" like strategy? That is, couldn't they ship CPUs that fundamentally are not decoding x86 ops, but some different ISA, and then layer a translation layer on top of it?

The Transmeta Crusoe used to do this, and I think the NVidia Denver cores did too?

I think fundamentally though this analysis highly depends on single-threaded performance being the bottleneck for most apps. A lot of sophisticated workloads are GPU or TPU driven, and so hand-waving away multi-thread performance, and treating single-thread performance as the end-all for client side performance I think is overemphasizing its importance.

Also, the "they don't control the stack" argument is wrong. Effectively, Intel/AMD + Microsoft acted as a duopoly, and if you toss in NVidia, the structure of DirectX and Windows is largely a cooperative effort between these OEMs. If Intel/AMD needed some fundamentally new support for some mechanism to boost Windows performance by 20-30%, Microsoft would work with them to ship it.

klelatti4• 6 years ago

The PC world has already switched architectures 32 bit to 64 bit already so its doable.

The big issue I think is if you are Intel / AMD why would you do this? Even if there are performance gains do you really want to undermine one of the things (backwards compatibility) that distinguishes you from the competition? Plus what would the new ISA be?

Plus Intel still has the memory of Itanium.

djtriptych• 6 years ago

As someone who's generally been tech-aware for decades, this seems like a revolution. I've never seen reviews like this. I keep buying AAPL. I think they're going to eat Intel.

fancyfredbot• 6 years ago

A lot of people are asking why Intel or AMD haven't produced a CPU like this, but that's not so interesting to ask because maybe that's something to do with the x86 ISA.

What about Qualcomm, ARM, and Samsung though? What's their excuse?

hocuspocus• 6 years ago

Maybe it simply doesn't economically make sense for Qualcomm and even less so for Samsung. Their SoCs equip a lot more entry-level or mid-range low-margin phones, compared to Apple.

There might be the need to make more powerful, desktop-class SoCs in the future if Google and Microsoft push for that. But I imagine the real competition will come mostly from the server market for now. Unless Nvidia starts making beefier SoCs, maybe the upcoming Orin.

sys_64738• 6 years ago

What do we know about the memory model? I see refs to not copying memory which suggests there isn’t even any L1 cache on die. Is this true? Anybody got a detailed arch diagram of the M1’s memory hierarchy?

bahmboo• 6 years ago

As a person who has written tons of machine and assembly code and dealt with decades of working directly with the cpu: this is a well written and accurate article.

nazgulnarsil• 6 years ago

Good packaging and TSMC's better than expected results are certainly a big part of the picture. TSMC: '5nm yielding better than 7nm.' Apple can put the higher leakage chips in mac minis where they can afford to pump more power through.

breatheoften• 6 years ago

I've been wondering what kind of hardware optimizations might be possible based on tagged pointers? If you know a memory location is uniquely referenced for example when you load or store ...

aclindsa• 6 years ago

So e.g. smaller ARM CPUs don’t use micro-ops at all. But that also means they cannot do things such as OoO.

Perhaps I'm picking nits, but the second sentence is not true. The dependency/resource-tracking and scheduling required for OoO execution do not depend upon using micro-ops.

da39a3ee• 6 years ago

If, in an alternate universe, the people who have designed the amazing hardware we have today suddenly switched to work on designing web backends of medium-sized tech companies, would they do a better job than the random mess of databases, services, microservices, HTTP APIs, GraphQL APIs, client-side logic, server-side logic, etc that we have today?

dirtypersian• 6 years ago

"RISC CPUs have a choice. So e.g. smaller ARM CPUs don’t use micro-ops at all. But that also means they cannot do things such as OoO."

I don't agree with this. What do uops have anything to do with ooo execution. I can easily make a CPU with no uops doing ooo execution. Unless I'm misunderstanding and the article is just saying smaller cores don't do ooo since they are trying to stay within a certain area/power footprint.

jet_32951• 6 years ago

Thanks, @socialdemocrat, that is a good intro for someone (like me) who doesn't understand hardware architecture.

socialdemocrat6• 6 years ago

Great! I thought there was many people who wanted some in depth discussion but which did not necessarily have a lot of prior knowledge about the topic. E.g. Anandtech gives a lot of great detailed info, but hard to read if you are not a regular reader of their website.

phendrenad2• 6 years ago

I still don't get why they didn't use RISC-V. Sure, they have an ARM license, but running existing ARM software on the M1 doesn't seem very useful. Why not use the superior ISA?

fomine36• 6 years ago

Why use different arch to iPhone/iPad? M1 borrows most design from A chip and they spent time to optimize software for Arm.

CivBase• 6 years ago

In real world test after test, the M1 Macs are not merely inching past top of the line Intel Macs, they are destroying them. In disbelief people have started asking how on earth this is possible?

I'm getting sick of this. The M1 is an impressive chip for sure, but it's ridiculous to compare them to the Intel chips in last year's MacBooks. Those chips were old, the cooling solution was terrible, and Intel had already fallen way behind AMD for the kinds of tasks you might actually use a MacBook for. The cynic in me thinks Apple intentionally handicapped the 2019 models to make the M1 look as good as possible... and it clearly worked.

Can we please stop comparing apples to oranges (pun intended)?

Like I said, the M1 is impressive - especially in terms of power efficiency - but we should be comparing it to the likes of an Intel Core i7-1185G7 or the imminent AMD Ryzen 7 5800U.

_s8vu4• 6 years ago

What are you talking about? The last gen Macbook Air and Pro had Ice Lake chips with Iris Plus graphics, why would that be not a fair comparison? Sure, the Air did have a terrible cooling system, but so does the new Air. The 2020 4-port 13” Macbook Pro that still continues to be sold as they’re the only 13” Macbooks that can be configured with 4TB SSD and 32GB RAM as of now, has a 4-core Ice Lake that Apple literally push to its limits to squeeze every ounce of performance they can, if you watched a review or two covering that machine. Linus Tech Tips complained that it was running too hot — not thermal throttling, just going really fast. And the M1’s GPU is like 2-2.5x faster than even those machines’ iGPU.

supernova87a• 6 years ago

I'm super curious -- since Apple is not marketing on Ghz and playing the Intel game, how do they deal with variable chip manufacturing yield? Is there a narrow band or minimum chip speed that they'll accept and toss anything performing below?

Does the SoC become so physically larger that yields also go down by quite a bit, and any defects on 5nm become much more troublesome?

sliken24• 6 years ago

Anyone wanting linux on the M1 there's now a patreon at https://www.patreon.com/marcan/

raiyu• 6 years ago

The whole m1 vs intel and AMD saga reminds me of innovators dilemma and the lesser referenced investors solution by Clayton Christensen.

In the solution book it basically details that everything goes through an ebb and flow of aggregation and disaggregation. This was often pointed out with Craigslist as the original aggregator and how many startups have been founded now to disaggregate it.

Interesting to read this article from that perspective. Intel and AMD disaggregated and found success for decades but now aggregating with SoC looks to yield massively better results.

Interesting to see certain business patterns continue to reappear.

Also shows that in tech no one has dominance if they don’t adapt.

pmontra• 6 years ago

Sure Intel and AMD may simply begin to sell whole finished SoCs. But what are these to contain? PC makers may have different ideas of what they should contain.

There used to be many competing CPUs with different instruction sets. I personally used z80*, 6502, 680xx, 80xx, Alpha, one from HP and who knows how many others. Add PowerPC and was Itanium a not x86 CPU? Then we almost standardized on one for a long time, plus ARM lately. No reason for we won't standardize on one SoC. It could be everybody buying only Apple computers (unlikely) or some company winning the forthcoming SoC wars. Or business as usual and stay on the current general purpose architecture forever, which is also unlikely given the optimization advantages of a SoC like the M1.

fractallyte• 6 years ago

So they have 'co-processors', like the Amiga, but on a chip!

Recall, this is what made the Amiga such a groundbreaking computer back in the 80s and early 90s: separate co-processors that handled graphics, sound, DMA, IO,...

It worked (for a while) because the Amiga was an integrated system of hardware-and-OS - exactly like Apple. Unlike the MS-DOS and Windows PCs of the time, there was no need to support third-party hardware.

Together with a really nice OS, the platform encouraged creativity and gave rise to a generation of coders, artists, and musicians.

So everyone: now you know what it felt like when the Amiga first appeared on the home computing scene!

Michael_Sieb• 6 years ago

Cant wait to see this chip in the 16-inch.

helsinkiandrew• 6 years ago

Sure Intel and AMD may simply begin to sell whole finished SoCs. But what are these to contain? PC makers may have different ideas of what they should contain. You potentially get a conflict between Intel, AMD, Microsoft and PC makers about what sort of specialized chips should be included.

It will be interesting to see what happens to the Wintel business in the years to come - is this the beginning of the end? If Apple can build a strong price/performance advantage in a way that can't be replicated by PC makers and, for example, start bringing out cheaper 'SE' versions of their laptops.

rocqua• 6 years ago

With out of order execution being apparently a big deal here, what are the odds of side-channel attacks based on this OoOE being found for this architecture?

warpspin• 6 years ago

The one thing that still puzzles me is, how that unified memory thing works and actually handles contention between GPU and CPU without slowing either down. There's not much information out there how it actually works.

Anybody has any details?

ralphc• 6 years ago

Couple of years back I bought a big gaming laptop to do ML and deep learning on, TensorFlow, Keras, all that. i7 and NVidia 1080, 8G of GPU ram. I know TensorFlow has been ported to Big Sur/M1, anyone know how well it performs with sharing memory between CPU and GPU?

zaro• 6 years ago

I don't understand why the bug fuss about M1. After all M1 is 5nm CPU. AMD Renoir is better than Intel for the same reason, it's 7nm while Intel can't get below 10nm yet.

So while M1 is probably a great CPU I expect its advantages will mostly vanish once AMD and Intel move to 5nm also.

lenkite• 6 years ago

So basically Intel shouldn't have abandoned Itanium.

zuhrik• 6 years ago

After analyzing the benchmarks I have a suspition that the apple compiler does some automatic parallelization and issues some instructions on the GPU, since the GPU shares the memory coherency with the CPU. That's why roseta2 performance is slower, as optimizing loops on the binary is harder. If they are not doing that, they should, as it will be something like an AVX512 for the poor energy budget. Just lunching a debate, as the wide decode with long pipeline smels like a Pentium4 crap or a miracle.

Karuhanga• 6 years ago

I suspect Intel will in the future have separate processors which can less painfully take advantage of more decoders, perhaps with a restricted instruction set?

Why is Apple's M1 chip so fast?

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