ASML EUV lithography machine could keep Moore’s Law on track

https://spectrum.ieee.org/high-na-euv

by mfiguiere • 3 years ago

206 181 3 years ago

spectrum.ieee.org

tgtweak3• 3 years ago

Is this the one that Intel is getting first dibs on for the next few generations? Looks like these fabrication paradigms generally work on Moore's law for some time before tapering off (S curve to some degree) but the discovery of a new paradigm can slow down the overall trendline if it takes too long to commercialize.

bloggie• 3 years ago

ASML currently has a market cap larger than Intel. That has nothing to do with their sales but puts into perspective how important this technology is relative to all of Intel's activities. TSMC has been reported as their biggest client (https://www.reuters.com/technology/asml-shares-fall-7-after-...)

zgluck• 3 years ago

Huh, wow.

ASML: $287B

AMD: $182B

Intel: $154B

nine_k• 3 years ago

Somebody noticed that progress is usually a stack of sigmoids, not an uneventful and plain upwards curve.

fotta• 3 years ago

Intel has purchased the high-NA EUV machines[0] but I can't find any source on exclusivity.

[0] https://www.reuters.com/technology/intel-orders-asml-machine...

knewter• 3 years ago

As I understand it, exclusivity with ASML comes solely from their limited production capacity. Just buy all the machines for the year.

TheUnhinged3• 3 years ago

Intel is getting the first prototype(s), in a few years from now. Then add a a year or two before those EXE’s are actually used for volume manufacturing.

No exclusivity, as it’s ASML business model to work fairly with all semiconductor manufacturers.

tgtweak3• 3 years ago

They have the prototypes now, and are talking about entering mass production 2H 2024 [1]. From what I read, Intel has already received and taped out 18A and 20A using these new high-NA machines [2]

Intel has announced that manufacturing of 18A-node chips will commence in H2 2024, six months ahead of schedule. According to a roadmap released last year, this node will be Intel’s first to employ high-NA lithography. It’s not clear whether this means that the next-gen EUV technology makes its debut in production a little earlier than expected. Last January, ASML CEO Peter Wennink told investors that he expected high-volume high-NA manufacturing to start in 2025 or 2026.

ASML high NA Credit: ASML ASML’s first high-NA system, the Twinscan EXE:5000, is fully production-capable, but chip manufacturers will initially use it for process development. The first unit will ship in H1 2023, with Intel on the receiving end. The US processor maker also placed the first order for the EXE:5000’s successor, the EXE:5200. The swift adoption of high-NA is an important element in Intel’s strategy to regain “unquestioned leadership” in the semiconductor industry by 2025.

[1]https://bits-chips.nl/artikel/intel-moves-high-na-node-up-6-... [2]https://www.tomshardware.com/news/intel-completes-developmen...

crote2• 3 years ago

Not going to happen. Remember, TSMC manufactures chips for Apple, Nvidia, AMD, Google, and a looot of other companies. They own about 60% of the cutting-edge fab capacity in the world, while Intel was basically an "also ran" during the transition to EUV.

ASML is never going to tie themselves to a single customer like that, let alone one which isn't even the market leader. High-NA is a massive technological change, and all the major players have already ordered their machines. Intel was simply the first to complete their order in a desperate attempt to avoid a repeat of their EUV debacle, but they'll receive their new toy at most a month or two earlier than their competition.

tgtweak3• 3 years ago

First dibs is not exclusivity, they simply were the first to order it and will be the first to receive the initial machines giving them a calendar advantage.

I assume these will be made available to Intel Fab customers as well at internally to Intel, since they are opening up 3rd party fabrication at a service offering.

martin_drapeau2• 3 years ago

I worked at Imec back in 2005 alongside the teams installing and researching the first EUV machines from ASML. Never thought they’d get it to work given the technological challenges. Laser-pulsed tin plasma, mirrors instead of lenses and vacuum exposure just to name a few! Glad they got it working so we can print smaller at scale.

throwawaylinux8• 3 years ago

What were the challenges you were seeing or heard were the biggest? The light source?

TheUnhinged3• 3 years ago

Everything was a challenge with EUV—the source, the vacuum, the mirrors, the reflective reticle, getting sufficient throughput…

yread• 3 years ago

Friend of mine worked for an asml supplier. He was working on adjusting the optical path based on how the laser going through a lens heats that lens up and changes its optical qualities. There are so many challenges we don't even think about

jacquesm3• 3 years ago

Building a modern semiconductor factory starts long before you can begin to think about the foundation. Minimizing vibration is included in thinking about the siting, seismic insulation of the building and the placement of just about everything in the fab itself.

Think 'boxes in boxes' to get maximum insulation. I also have a friend who works in this industry and he once joked that they have an almanac built in to deal with moon tides and while it is a funny joke you have to wonder if there isn't going to be a time when even that sort of effect will have to be accounted for. Amazing stuff.

ASML is one of a short list of Dutch companies that I'm super proud of, they keep on innovating no matter how extreme the challenges are. The moat they have is incredibly deep.

magicalhippo• 3 years ago

When you go to the extremes those tiny details suddenly aren't tiny details anymore. As a semi-random example, a significant source of noise in LIGO, the gravitational wave detectors, is the push of photons striking the 40kg mirrors[1][2].

[1] https://arstechnica.com/science/2020/07/ligo-is-so-sensitive...

[2] https://arxiv.org/abs/2002.01519

esperent• 3 years ago

EUV necessitates an entirely new way to generate light. It’s a remarkably complex process that involves hitting molten tin droplets in midflight with a powerful CO2 laser. The laser vaporizes the tin into a plasma, emitting a spectrum of photonic energy. From this spectrum, the EUV optics harvest the required 13.5-nm wavelength and direct it through a series of mirrors before it is reflected off a patterned mask to project that pattern onto the wafer

This is incredible and feels like the most sci-fi sentence I've read in a long time.

It's unbelievable to think that this works, not just in a lab, but in commercial systems that will produce hundreds of chip wafers an hour (>100 anyway, they didn't clarify further).

sbierwagen• 3 years ago

It's also terribly inefficient. EUV "mirrors" eat 30% of the incoming light. Since they have such a narrow reflective range and the source light isn't collimated or coherent, you have to use a bunch of them. By the time you're at the mask, you've lost 96% of the light. As a result:

Hynix reported at the 2009 EUV Symposium that the wall plug efficiency was ~0.02% for EUV, i.e., to get 200-watts at intermediate focus for 100 wafers-per-hour, one would require 1-megawatt of input power

https://en.wikipedia.org/wiki/Extreme_ultraviolet_lithograph...

It's an damn good question of how much further this can scale. EUV photons are a lot more like x-rays than they are visible light. They're energetic enough now they're inflicting ionization effects on photoresist material, blurring the exposed area with secondary electron scatter. The fundamental limit of electronic transistors, ones made out of single molecules, are going to be tough to make with lithography.

_hypx3• 3 years ago

The final challenge will be cost: With every iteration, costs increase dramatically. At some point, it simply ceases to make sense to scale down transistors any further.

tlb• 3 years ago

Still, 1 MWh is a tiny fraction of the power those 100 wafers worth of chips will consume in their lifetime. So if we can reduce power consumption with smaller features, it's worth using more laser power.

fnordpiglet3• 3 years ago

I’d note that quote is 14 years old - hopefully there’s been some R&D over that time!

ben_w4• 3 years ago

That makes me wonder (as someone who has merely heard of the two technologies and knows nothing much about either beyond the Wikipedia page) why it's not using a free electron laser?

Aren't those tuneable to any wavelength down to X-rays?

winternewt2• 3 years ago

I wonder what the possibilities for a fundamentally different manufacture method are. For example, what if we could program a layout into DNA and have biological agents construct it?

HPsquared• 3 years ago

In other words, 10 kWh per wafer - a couple of dollars per wafer in energy costs.

rsweeney21• 3 years ago

Came here to make the exact same comment. I can't help but feel like some day we will forget how we were able to make such amazing machines.

Agathos• 3 years ago

Two must watch videos about the whole process:

https://youtu.be/5Ge2RcvDlgw

https://youtu.be/pfU20SAR21A

(Typed on a device made by this process, which I still don’t quite believe.)

NortySpock2• 3 years ago

Twice. They have to hit the molten droplet twice.

Once "gently" to deform it briefly into a concave shape, and the second, harder pulse to actually activate the droplet to emit extreme ultraviolet light

Asianometry on EUV. Skip to 10m50s. https://youtu.be/5Ge2RcvDlgw

fnordpiglet3• 3 years ago

Anyone who reads these descriptions and doesn’t realize this is literally the magic of sorcerers predicted in our fantasy lore have lost the ability to dream. What an amazing time to be alive.

szundi• 3 years ago

For everyone to understand: pew pew, not just pew

audunw2• 3 years ago

Asianometry is an amazing channel for topic like this. Also check the video on water for chip manufacturing. You’d never think there so many interesting challenges with something so mundane as water.

Modern chip manufacturing is basically black magic.

Cyph0n• 3 years ago

Timestamped link: https://youtu.be/5Ge2RcvDlgw?t=10m48s

fennecfoxy• 3 years ago

Not only do they hit it twice, but they're also depositing and hitting it twice _50,000_ times every second!

https://www.asml.com/en/technology/lithography-principles/li....

Just absolutely insane engineering going on there.

nntwozz2• 3 years ago

If you like that and want to know more Asianometry did a deep dive on this process:

https://youtu.be/5Ge2RcvDlgw

A short video showing the laser in action:

https://youtu.be/NHSR6AHNiDs

ksec• 3 years ago

This is incredible and feels like the most sci-fi sentence I've read in a long time.

And that is sad part of so called "Tech" today. Zero appreciation of it outside of the minorities.

They are doing is on a massive scale, extreme precision, high cost of electricity, insane difficulty in both designing chips and production.

And yet HN thinks all the hardware chips today are over priced and absurdly expensive.

incompatible• 3 years ago

It's a bit worse than "zero appreciation" in some cases, it's people using the results from hundreds of years of advances in science and engineering to proudly post their anti-scientific viewpoints.

mitthrowaway23• 3 years ago

HN will also happily exclude companies like ASML from their definition of a "tech" company, because most of their value doesn't come from their software IP.

throw0101a• 3 years ago

And that is sad part of so called "Tech" today. Zero appreciation of it outside of the minorities.

This has always been true of technology.

Do you think most people cared about how a steam engine worked, or simply that it allowed them to go faster than a horse? Or the telegraph, radio, television, the internal combustion engine, etc.

jasonwatkinspdx• 3 years ago

Even more crazy that process runs at 50khz, that is vaporizing 50,000 droplets per second. This is necessary because the overall efficiency is really poor vs the energy density they need on the chip to react with resist.

zeristor2• 3 years ago

This raised all sorts of questions I was going to ask about the Physics, but I found this OpenAccess paper I’ll go through:

“Physics of laser-driven tin plasma sources of EUV radiation for nanolithography” (2019) https://iopscience.iop.org/article/10.1088/1361-6595/ab3302

zapkyeskrill• 3 years ago

In a moment of brain fart I imagined this process happening on the end device, us needing to /refuel/ the devices every now and then ...

arethuza• 3 years ago

There are some fascinating videos on YouTube from Zeiss, who do the optical systems for the ASML machines:

https://www.youtube.com/watch?v=z6c3vzIGo9o&t=632s

WeylandYutani• 3 years ago

Well it did take them 30 years to get working and lots of money.

That's why ASML doesn't have any competition: everyone else gave up.

nntwozz2• 3 years ago

Moore's law was never really "on track". Asianometry nailed this topic beautifully in this video:

https://youtu.be/nRJgvX6P8dI

dcormier• 3 years ago

I recently had an opportunity to chat with a machinist who works for a shop that makes some parts for ASML’s machines. He showed me a picture of a couple of parts he finished that day. He said they weighed about a hundred pounds sitting there on the table, but at the acceleration they experience in the machine, they weigh roughy the same as a Toyota Tacoma.

iamgopal2• 3 years ago

We make centrifuge, 1000g is routine for most centrifuges.

TheUnhinged3• 3 years ago

Now imagine all of this with a precision of a few nanometers…

abwizz5• 3 years ago

any tipps for centrifuge related youtuber content?

hotpotamus• 3 years ago

I can't imagine that what I think of as a machinist - a human who picks up parts and places them into machine tools and adjusts settings - is who makes parts for semiconductor manufacturing machines. I'm guessing the title has a lot more to do with CNC/automation these days?

SomeCollegeBro• 3 years ago

You kind of just described the job description of a modern "machinist". It's far more of a job regarding the machine itself (CNC in this case) and it's setup, versus the part itself being made. A mechanical engineer or manufacturing engineer deals moreso with that. Machinist is more synonymous with "operator" in my field.

shrubble• 3 years ago

FWIW the Bridgeport milling machines could hit 1/10,000th of an inch which is 25 microns of accuracy many years ago. DRO and precisely controlled steppers on newer machines can do much better.

The Pratt and Whitney Jig Borer was hitting 50 microns... in 1928. See https://img.photobucket.com/albums/v337/johnoder/8PiecesofIr...

lockhouse4• 3 years ago

Processing power is fine these days. It’s memory that I feel has stagnated.

The standard computer configuration has been stuck at 8 GB of RAM and 256 GB of SSD storage forever.

cobalt• 3 years ago

build your own, it's not that expensive to 4x both those numbers

wtallis5• 3 years ago

"The standard computer configuration" stopped referring to desktops long before 8GB DRAM + 256GB SSD went mainstream.

sbrother2• 3 years ago

Processing power is fine these days.

I don't know, I've been working with LLMs a lot recently and for the first time in a while I am wishing I had access to much more compute than I do. Imagine having the power of a H100 locally without having to pay thousands of dollars a month.

rodoxcasta• 3 years ago

For inference, at least locally, the bottleneck is usually the memory bandwidth (and quantity, of course).

I hope that AI hype lead us to more memory and more memory bandwidth, because they are really lagging behind computer power increase from like 15 years already.

FpUser• 3 years ago

At home (which is also my workplace) all my PCs are at 128GB. The server is 512GB. Laptops are 64GB. RAM has not been stagnated. Just buy what you need. To get it cheap for example for laptops I would buy smallest configuration (RAM and SSD wise) but with good CPU. I would then throw out old RAM and SSD and replace with the ones I buy separately. Way cheaper this way. PCs and servers are assembled from parts. Again I just order what I need and then let custom PC maker nearby assemble it for me.

jeffbee2• 3 years ago

Get used to it. The memory wall is coming and if you are in the industry it's possible that within your career you may need to adapt to falling DRAM-to-core ratios.

RetroTechie3• 3 years ago

The memory wall arrived decades ago. That's why caches were invented (which don't solve the problem, just soften the blow).

One approach would be to snip RAM in as many pieces as you have cores, and attach each piece locally to a CPU core. Say eg. 1k cores each with 1/1000th of total RAM, accessible at L1 cache like speeds. Giving you crazy-high (combined) memory bandwidth. I know, there exist some IC's that actually do this.

Problem is such a setup is not suitable for all types of computation. For data structures that require individual cores to access other cores' local RAM, you still need some communication protocol (+ latency, bringing you back to square 1).

And we haven't quite figured out how to program such a beast in software developer-friendly way.

Hence the usual approach of "all RAM in one pile, connected via a fat pipe to a heap of CPU cores".

cypress662• 3 years ago

I'm not sure what "standard computer configuration" means. Maybe you mean a budget laptop? Your typical new gaming desktop build is 32GB, and for a workstation probably 64GB.

I think you can get a 2TB ssd for like a 100 bucks nowadays. They are dirt cheap.

automatic61313• 3 years ago

I think you can get a 2TB ssd for like a 100 bucks nowadays. They are dirt cheap.

Unless you're paying Apple for it :^). Hope you like 12x markup to go with your 1TB SSD :^)

lockhouse4• 3 years ago

Gaming desktops are not even close to being a standard computer configuration and you know it.

I’m talking about the typical computer you’re going to find in a big box store or the default configuration on a website.

Yes you can add an SSD yourself for that price but the markup for configuring it at purchase is considerably more than $100. I’m not talking just Apple when it comes to this, Dell, Lenovo, HP, Microsoft, and just about everyone else do it too. RAM is even worse now that many (most?) laptops have it soldered in, so there is no DIY upgrade after you buy.

Tade0• 3 years ago

Out of curiosity I looked at the store I get my laptops etc. from and grouped by RAM, the laptop category looks like this:

8GB - ~350

16GB - ~1060

32GB - ~550

I don't know about desktop PCs, but in laptops 8GB is not mainstream any more.

abwizz5• 3 years ago

it's gotten better somewhat.

thou, 8gigs are overly common (and overrepresented in regard to your market analysis) as most consumers (and enterprises) tend to buy the low-end config unless it's absolutely necessary to spend more.

mikewarot2• 3 years ago

Von Neuman's architecture has run out of steam. The fact that most transistors in a computer at any given moment are idle seems to be a huge waste. What if you could just have a computational fabric that lets you have one instruction per cell, and run whole programs in parallel?

FPGAs do that, but the "smart" routing fabric in them makes compiling code to them take hours or days.

If you eliminate the switching fabric on an FPGA, you are left with a grid of Look Up Tables (LUTS) each connected to their neighbors. The result is a Turing Complete computer that works exclusively in parallel.

rowanG0774• 3 years ago

Why aren't we going electron lithography? As a laymen I think it should easily be able to surpass EUV in terms of resolution. I would imagine there are very good reasons why we aren't seeing it.

barelyauser• 3 years ago

You may be able to surpass it in resolution but you can't surpass it in terms of throughput.

_hypx3• 3 years ago

Electrons are electrically charged, so a beam of electrons will interfere with itself. The only way around this is to have a very narrow beam, but that kills throughput.

bilsbie• 3 years ago

How about muons then?

icapybara2• 3 years ago

Well put.

crote2• 3 years ago

Because it has absolutely awful throughput. Electron-beam lithography has an output measured in days per wafer. Meanwhile, EUV can easily output 150+ wafers per hour.

When the choice was made to go for EUV, E-Beam was actually the most mature technology available for next-gen lithography - but it just wasn't economically viable. The technology has remained in development over the years, but not a lot has changed yet.

If you want to know more about the topic, I can strongly recommend this video from Asianometry: https://www.youtube.com/watch?v=RmgkV83OhHA

rowanG0774• 3 years ago

I mean if the machine is 100x cheaper to buy/maintain it might still be worth it. The price for EUV in TCO per machine is insane.

zogomoox• 3 years ago

If China can't get their hands on EUV, E-Beam seems a logical step for them to develop anyway.

wuming22• 3 years ago

Peak applications require the latest and most powerful tech. With it’s colossal trail of pollution from manufacturing.

For the rest I often wonder if would not be better for the environment to re-purpose older, already made tech.

Plenty of embedded systems grinding on for a long time.

And user facing applications lack one thing: public stats of peak system usage. When confronted with a new purchase we should be handed over a sheet of our own and peers statistics. Producers and service providers have them anyway.

WantonQuantum2• 3 years ago

Agree 100%.

In an ideal world, the cost of everything we buy would include the real costs of pollution (including greenhouse gases), depletion of common resources such as water, and recycling or otherwise accounting for the environmental impact after use.

As you say, suddenly those 5 year old phones and computers would be economically attractive again. With a knock-on effect that websites and software would cater more for older devices.

But we don't live in an ideal world. We live in a literal Tragedy Of The Commons (https://en.wikipedia.org/wiki/Tragedy_of_the_commons).

Note that I'm not at all saying that we shouldn't have companies like ASML researching processes like this - more efficient chips are good for the environment and the economy.

oezi• 3 years ago

Lots of old foundries are still producing old chips.

wuming22• 3 years ago

But we are not reusing them.

RetroTechie3• 3 years ago

Try & view compute power as order of magnitude, vs. what useful things can be done with it.

Something containing ~100k transistors, ~10KB RAM & flash, running at a few MHz in a power envelope measured in milliWatts, has production cost (and environmental footprint) of practically 0 these days. But still enough brains to control your washing machine, monitor solar panel or open garage door w/ remote.

A few steps up & you have epaper equipped tablet that allows you to read books, simple games or check weather forecast, doing so for days or weeks on battery power.

On the other end of the scale you have datacenters, supercomputers & their energy + manufacturing footprint. With desktop PC's, laptops & game consoles somewhere in between.

When choosing between:

a) Apply budget, see how much CPU, GPU, RAM etc. that buys you, and deal with physical size + power draw / thermals, these days I go for

b) Pick physical size + power budget, see what kind of CPU / GPU / RAM etc you can shoehorn in there @ what cost, and just deal with the limitations of such device (if perceived as limiting, that is).

It's amazing what a Raspberry Pi sized computer (or further down, a modern uC) can do these days. Lean software does exist. No clunky desktop needed if you just want to play PacMan. :-)

Qwertious2• 3 years ago

For the rest I often wonder if would not be better for the environment to re-purpose older, already made tech.

It is. https://www.lowtechmagazine.com/2020/12/how-and-why-i-stoppe...

beebeepka• 3 years ago

What surprised me the most is how little telemetry they have, almost none of it in real time. I guess the industry is used to just eating up the cost defects but it was mind blowing (or eye opening) to me.

apienx• 3 years ago

The industry's currently shipping chips based on the 3nm process. I understand that it's mostly a marketing term (i.e. non-standardized), but I assume the actual transistor channel is within that order of magnitude.

Knowing that a silicon atom is larger than 0.1 nm, how can we possibly keep Moore's Law on track? It feels like we're close to hitting fundamental limits.

Any insights would be much appreciated. Thanks!

dougmwne2• 3 years ago

Sure, we are close to the end of silicon semiconductor improvements. And Moores law could be near its end. In fact the price per transistor has not been dropping recently, so it may be over already.

If there’s hope for the future, it’s that there are many other computing technologies besides traditional silicon that show potential, so maybe the torch will be passed to quantum, or superconductors or dna or something else.

ly3xqhl8g94• 3 years ago

We are ridiculously far from physical limits in our current artificial computers (both theoretical [1], and practical [2]). For more technical details see Jim Keller: [3] [4] [5].

[1] https://en.wikipedia.org/wiki/Limits_of_computation

[2] The ~12 watts computer inside each living human adult skull (and perhaps each eukaryote cell [6]) is still the state-of-the-art, for quite some time.

[3] 2021, Jim Keller: The Secret to Moore's Law, https://www.youtube.com/watch?v=x17jIKQf9hE

[4] 2019, Jim Keller: Moore’s Law is Not Dead, https://www.youtube.com/watch?v=oIG9ztQw2Gc

[5] 2023, Change w/ Jim Keller, https://www.youtube.com/watch?v=gzgyksS5pX8

[6] Our computers aren't yet able of polycomputation, where the computation topology, data, and functions depend on the observer, instead of computation in a passive implementation, once done forever set in s̶t̶o̶n̶e̶ silicon, 2023, Michael Levin, Agency, Attractors, & Observer-Dependent Computation in Biology & Beyond, https://www.youtube.com/watch?v=whZRH7IGAq0

cubefox7• 3 years ago

Physical limits don't matter much when economic limits (transistor cost) are reached much earlier. What matters is not transistors per chip area (Moore's law) but FLOP/s per chip cost. Also FLOP per chip power draw.

andy_ppp• 3 years ago

How does 13.5nm light etch features of 7nm and lower? I can sort of see how ultra pure water can focus the light (immersion lithography) and multi patterning (I’m not sure how this works really, I would have thought shining light through two masks would make things even more blurry). When the photon hits the silicon why isn’t the dot 13.5nm?

glic3rinu2• 3 years ago

masks dont have the actual shape, but shapes accounting for wave interference patterns that will end up producing the final shape when EUV light passes through. I believe the process of comming up with the correct intereference pattern takes weeks of supercomputing.

abwizz5• 3 years ago

sounds legit, any sources?

atq2119• 3 years ago

It does seem magical.

The one thing I can answer is that multi-patterning does not shine light through two masks simultaneously. Instead, it consists of multiple separate steps.

I think for the rest, the point is that light arriving on the waver is not a binary thing, but due to refraction and self-interference light arrives in variable intensities. So within difficult constraints, this allows you to control the area in which the intensity is below our above certain thresholds. I assume that if you then manage to control the chemistry just right, you can then produce features that are smaller than the wavelength of the light -- under severe constraints of what shapes you can produce. You definitely do not get to produce an arbitrary bitmap of sub-wavelength pixel size.

abwizz5• 3 years ago

good question, was also wondering.

then again, it's called the wave-lenght, not the wave-width

dist-epoch• 3 years ago

You just use the "edge" of the light to cut.

If you drag a baseball bat through sand, the edge of the cut "channel" is much sharper and narrower than the baseball bat.

Now offset the baseball bat a bit and draw another line which is partially overlapped over the first one. You will get the intersection of the two baseball bat wide channels, but it will be much narrower.

javaunsafe20193• 3 years ago

One layman question here maybe someone with better knowledge of the field can answer: could it make sense at some point to work without masks and lights and have only large scale laser arrays that write the structures directly but in the smallest possible scale (electrons)? Wouldn’t such an array be more energy efficient, be able to acquire smaller scales and trough the parallel process at some point be as fast as current systems using masks + light?

dermesser3• 3 years ago

This is called electron beam writing, and is done routinely in research settings and to write the lithography masks, but does usually not have the required throughput for a production line. The upside of mask-based lithography is that all structures are exposed at once.

javaunsafe20193• 3 years ago

Thank you for your answer - that’s why I thought about parallel beams in a big scale.

audunw2• 3 years ago

You would think you can make the lithography faster with electron beams by just having many beams in parallel. But as far as I understand that’s doesn’t really work if you try to have too many beams: keep in mind that the electron beams would be extremely negatively charged. So they’ll repell each other if they get too close.

javaunsafe20193• 3 years ago

So we need just more space - like a football stage to have 150+ parallel lasers each one producing one waver per hour?

brancz• 3 years ago

Is there any indication that it’s possible to build subatomic size transistors? Last I checked the data, transistors are already only a few atoms in size (silicon and carbon atoms are somewhere in the 0.3nm range), and it was a widely held opinion that it would stop at that if not much sooner. That would keep Moore’s law alive for a bit longer at best but the end does seem in sight.

Even considering all of that the economics seem to have already stagnated in cost for performance.[1]

[1] http://databasearchitects.blogspot.com/2023/04/the-great-cpu...

automatic61313• 3 years ago

Bear in mind, when silicon foundries say they have an Xnm process, nothing in that process is actually Xnm. TSMCs 2nm process does not make transistors 2nm wide[1]. They are in fact, approximately 40-50nm wide. The process number is a marketing number, and what changes each generation is actually transistor geometry (here you'll see terms like FinFET and GAA transistor and such, plus some process improvements that cause "half" generations)

[1]https://en.wikipedia.org/wiki/2_nm_process

But yeah, the fact that latest process nodes actually increase in cost is why people say "Moore's law is dead". Performance improves, but to keep the trendline roughly exponential, many things have had to give since the late 2000s. Such as: cost per wafer, power usage for max performance etc.

oznog• 3 years ago

Moore's Law is not engineering, it's economics.

The limits of physics can be surpassed with parallelization.

Moore's law is a reflection of the private and business market's desire/need for ever greater efficiency.

There is no limit.

ASML EUV lithography machine could keep Moore’s Law on track

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