AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome

https://www.anandtech.com/print/14525/amd-zen-2-microarchitecture-analysis-ryzen-3000-and-epyc-rome

by pella • 7 years ago

335 182 7 years ago

keyle2• 7 years ago

I find these articles incredible, but then I remember I work and live on a Mac. And I can't wait to pay 5K for the content of one of those articles published 2 years ago.

kbenson2• 7 years ago

And I can't wait to pay 5K for the content of one of those articles published 2 years ago.

Err, "can't wait" as in "it will be awesome when it arrives" or as in "I'm not going to wait for that, stupid Apple"?

kyriakos3• 7 years ago

I think the OP sarcasm was obvious.

thirdsun3• 7 years ago

Same here. I'd love to build a Ryzen box, and actually I'll do so for gaming, but my primary computer has to run macOS and unfortunately that requirement comes with a significant price tag, in addition to outdated hardware.

heyoni3• 7 years ago

Can’t you do hackintoshes with Ryzen?

Nexxxeh• 7 years ago

You can build a kick-ass Mini-ITX Ryzen box for less than a Mac monitor stand. Why not both?

pornel• 7 years ago

I did it, and it's great. It's possible to get Ryzen + GTX 2070 for a price of a Mac Mini. Of course it's a big ugly box, but it plays latest games without a hitch, even on 120hz/1440p "Ultra" graphics settings.

nabla9• 7 years ago

Apple hardware functions as a software protection dongle. If you want to use Apple software you must buy a dongle.

Synaesthesia• 7 years ago

Except if you hackintosh

Ragib_Zaman• 7 years ago

I guess I was being ridiculously optimistic hoping for the 16 core chip to be around the $600 mark :(

CriticalCathed• 7 years ago

750 is pretty close at least.

jchw3• 7 years ago

On the other hand, a 12C with a handsome IPC improvement from last generation at $499 feels pretty tempting to me...

gravypod4• 7 years ago

You can also buy into TR4 Threadripper 1950x for ~$500 [0]. I'm using one to write this post. It's a great system and you can likely buy used for cheaper than $500. I'm also assuming this price will fall further once they announce another TR4 chip.

[0] https://www.amazon.com/AMD-Threadripper-32-thread-Processor-...

DuskStar2• 7 years ago

12C with 64MB cache for $499 is looking more and more like the sweet spot to me, too.

wmf4• 7 years ago

Considering that Intel charges almost $600 for their top 8-core, yes, that would be ridiculous. There were some leaked/rumored prices for Ryzen 3xxx and Navi that were way too low and I didn't understood why AMD would almost give away such good products; the simple truth is that they won't.

reitzensteinm4• 7 years ago

They're not just adding more cores on because the processes have improved allowing for more on the same silicon.

The complexity of the chip is higher than the previous models, with three dies under the hood instead of one. The high end chips are closer to Threadripper than they are to the models they're replacing.

I think $750 is still a ridiculously good price, and Intel's feet are being held to the fire.

celrod• 7 years ago

The 1950X cost $1000 2 years ago, and it looks like you can pick them up for $500 now. Both are 16 cores with two chiplets.

1950X advantages:

  - 4 memory channels vs 2
  - 64 PCIe lanes vs 16-4-4

3950X advantages:

  - 64MB of L3 cache vs 32MB
  - DDR4 3200 vs DDR4 2666
  - The PCIe lanes are 4.0 vs 3.0
  - 3.5Ghz base clock vs 3.4
  - 4.7Ghz boost clock vs 4.0
  - 15% better instructions per clock
  - Full avx2 instead of emulating with two 128-bit units
  - 105W vs 180W TDP

The 3950X sounds like quite the improvement! Definitely a great deal IMO.

dis-sys• 7 years ago

I think $750 is still a ridiculously good price

Threadripper 1950x comes with the same core count, more memory channels, more PCI-E lanes and more memory. You can grab one for $499 from amazon.

kyriakos3• 7 years ago

8C 16T for 329 at 65w sounds like an incredible value for money for a budget workstation.

zanny• 7 years ago

To be fair 8 core 16 thread Ryzen chips could be had for as little as ~$200 for years now. With this release the respectable 2700X will probably fall pretty low in price till stocks run out.

larzang• 7 years ago

It almost makes me think the TDP of either the 3800x or 3700x is a publishing mistake. 3.6/4.4 to 3.9/4.5 on the same hardware can't possibly require such a dramatic voltage increase to go from 65w to 105w.

If it does, it means the process is struggling to produce chips at that speed, so the headroom is incredibly low and you can forget about overclocking.

m0zg• 7 years ago

I bet there will be such chips. They'll just have a few cores disabled. It's not like they make a separate die for every core configuration - that wouldn't make sense.

DuskStar2• 7 years ago

So in other words the $499 12C/24T 3900X?

292355744930110• 7 years ago

The Ryzen 7 1800X, the Zen flagship was $499. The Ryzen 7 2700X, the Zen+ flahsip was $329.

That was a 34% decrease in cost for comparable models after 1 generation. If that trend follows then the comparible Zen2+/Zen3 model will only be around $500. So, hopefully you just need to wait a year.

paulmd4• 7 years ago

The 2700X price cut occurred in the context of Intel releasing a 6C12T processor for $350 that kept up with AMD's $500 processor. i.e. very close in multithreaded performance and easily beating it in single-thread.

That's not going to happen this time around. Intel doesn't really have a response to 16C consumer processors. Best thing they can do is release the 10C chip they're working on... probably at $500 again. And they will be behind the 12C version that AMD has at $500 already.

The only similarly aggressive move that Intel could even make would be to drop 10C to the $350 segment (perhaps with Hyperthreading disabled), which would be a massive blow to their margins.

craz82• 7 years ago

It looks like Microsoft is adding code to Windows to schedule threads in a way that works with this configuration of cores and CCXs

Is/has Linux added similar code

Are we calling this Mini-Numa or something else?

shereadsthenews4• 7 years ago

Why would we call it “mini”? It is straight up NUMA.

wmf4• 7 years ago

It's not NUMA since the distance from all the cores to main memory is the same (uniform).

wmf4• 7 years ago

I would call it a form of Non-Uniform Cache Architecture (NUCA). Linux definitely knows the cache topology and the scheduler is NUMA-aware but I don't know if the scheduler takes cache topology into account. It seems like it would be a small change to track L3s instead of NUMA nodes.

microcolonel3• 7 years ago

It's NUMA, just like usual. The difference is the exact topology, and the real difference in latency (which changes the cost function of accessing from a different node).

floatboth5• 7 years ago

The CCXes aren't NUMA, they all have the same access to memory, no system would show multiple NUMA domains on a desktop Ryzen.

Only Threadripper and EPYC are NUMA.

consp3• 7 years ago

> Is/has Linux added similar code

Yes, in 4.15 patches emerged for TR/Epyc and waaaaaay back in 2.6 it had scheduler domains which can do the same thing.

shereadsthenews4• 7 years ago

The BTB was the real problem with Naples and the reason it sucked on non-trivial, branchy, pointer-chasing workloads like MySQL. With the improved branch prediction resources I’ll be interested in head-to-head of this rig vs. a Kaby Lake (or later).

ahartmetz• 7 years ago

Sounds interesting and I don't recall reading that before - can you point to some online article about it?

jnordwick3• 7 years ago

Also AMDs often smaller cache sizes, which still seems to be a problem if you compare to ice lake and above.

opencl5• 7 years ago

What? Zen/Zen+ had larger L1 icache than Intel, same size L1 dcache and L2 and L3. Zen 2 actually decreases the L1 icache to 32KB but in exchange increases L1 associativity, micro-op cache size, BTB size, and L3 size.

wahern2• 7 years ago

Anybody expect 7nm processes to result in longevity issues? As far as I understand (and IME) the first components to fail are capacitors. Might that begin to change?

Apropos the article, I'm trying to convince myself to build an EPYC 3201 server now rather than waiting for the Zen 2 version, for which I presume I'd have to wait until October or November at the earliest.

ngold• 7 years ago

First generation anything is not as good as it's going to be.

jdsully2• 7 years ago

Up until recently every CPU generation was on a brand new node - there was no second gen on the same process. We never had reliability issues with CPUs before.

baybal23• 7 years ago

I think, electromigration will still kill the chip earlier than individual device failures.

It was Intel is said to switched to cobalt wiring in latest node, and seems to be paying dearly for that. TSMC and others seem to go the conventional road and continued to perfect the salicide for smaller nodes without any issues.

dfrage2• 7 years ago

Officially, Intel says 10nm has lithography problems. They did try a more aggressive node than TSMC's first "7nm", entirely using 193nm UV, and were the only company to attempt Self-Aligned Quadruple Patterning (SAQP) for the top metal layers.

microcolonel3• 7 years ago

It was fun seeing their materials refer to their branch predictor as a TAGE predictor. I remember hearing about the original paper for that when I was too young and inexperienced to focus long enough to understand it; then I saw a TAGE predictor show up in Chris Celio's BOOM repository, and I read it through.

If what AMD says is true, the new (for them) TAGE predictor in their industry-leading microarchitecture having 30% fewer branch mispredictions than the last, it feels very cool that one can read and somewhat anderstand the operation of a similar predictor in the leisure hours of a few days.

Also those caches are huge, wow.

kjeetgill• 7 years ago

It took a little hunting, is this the paper? http://www.irisa.fr/caps/people/seznec/JILP-COTTAGE.pdf

gpderetta• 7 years ago

Interesting; Intel is rumored to use TAGE but it was never confirmed officially. AMD claimed to use a perceptron based predictor in the past.

emn13• 7 years ago

They still will, just for L1 only; TAGE is for the lower levels.

walterbell• 7 years ago

... for the issues to which AMD is vulnerable, it has implemented a full hardware-based security platform for them. The change here comes for the Speculative Store Bypass, known as Spectre v4, which AMD now has additional hardware to work in conjunction with the OS or virtual memory managers such as hypervisors in order to control. AMD doesn’t expect any performance change from these updates.

Which Intel CPU generation will have hardware fixes for these Spectre variants?

baybal23• 7 years ago

I guess it will score it a lot of datacentre business. Not so few big "cloud" providers still run completely bare with regards to microcode patches, and some very likely do so intentionally.

masklinn• 7 years ago

What do you mean by "run completely bare with regards to microcode patches", that they don't apply microcode patches & errata?

cm21872• 7 years ago

Is it still the case that an AMD core is less powerful than an Intel core for the same frequency? I understand that AMD is making it up with more cores but in a cloud you get charged per core. Can a cloud substitute an Intel for an AMD cpu?

indolering• 7 years ago

It will take years: https://www.wired.com/story/intel-meltdown-spectre-storm/.

psnosignaluk• 7 years ago

$499 for 12C/24T on the 3900X? $399 for 8C/16T on the 3800X? Those prices make this a very tempting chipset on top of the promised performance being touted by AMD. Looking forward to seeing the reviews and news on X570 boards. Hopefully the manufacturers will be plugging in decent features to match their threats of massive price hikes on AM4 boards with the new chipset.

sliken• 7 years ago

Rumors claimed there would be a 3700 that was 8c/16 64 watts and only slightly slower clocked than the 3700x. It was also supposedly $200 or so (the 3700x is $329).

Here's hoping it comes out, looks like a great CPU for a relatively cheap desktop.

penagwin3• 7 years ago

If the 3700x is $329 I would bet on the 3700 being around $250, at least at launch. ~$80 cheaper is how they currently have it priced, 200$ for a slightly lower clockspeed seems too cheap, and it'd cut into their 3600(X) range.

CoolGuySteve2• 7 years ago

For a single GPU machine, I’m not sure what the use case is for X570 over a much cheaper B450 board. Most games currently aren’t GPU-bus bandwidth limited (or rather the GPU itself is the bottleneck) so I suspect PCIe 4.0 won’t impact benchmarks much.

tutanchamun• 7 years ago

Since 2 lanes of PCIe4 are as fast as 4 lanes of PCIe3 I think it can make sense for more IO if you don't want to go for Threadripper. On top of that the motherboards I have read about thus far have better VRM setups for the CPU so for overclocking that could make sense as well.

TazeTSchnitzel4• 7 years ago

You do have to be careful that the B450 board you buy can handle the power requirements.

kllrnohj5• 7 years ago

On all of these the GPU is directly connected to the CPU and there is no chipset in the way.

The benefits of X570 over B450 therefore have nothing to do with GPU performance but instead would be either overclocking capability or, more significantly, I/O to everything else.

B450 only provides 6x PCI-E 2.0 lanes and 2 USB 3.0 gen 2. That's not a lot of expansion capability, especially with nvme drives. Want 10gbe? Or a second nvme drive? Good luck.

X570 gets to leverage double the bandwidth to the CPU in addition to being more capable internally. So you'll see more boards with more M.2 nvme slots as a result, for example. And thunderbolt 3 support. Check out some of the x570 boards shown off - the amount of connectivity they have is awesome. That's why you'd get x570 over b450.

ivl• 7 years ago

I'd agree you probably won't see much of a performance gain once things are loaded when comparing B450 to the X570 boards, but using a PCIe 4.0 SSD will very likely improve boot and load times.

(I'm fairly certain for most gaming workloads, the bandwidth increase will only come into play when getting closer to 4k 144Hz, which is unlikely to be pushed out by first gen PCIe 4.0 GPUs.)

fapjacks2• 7 years ago

... If you can find any. I still can't find anyone to sell me a handful of AMD's embedded SoCs. I don't want to buy them on a board. I want to buy the chips themselves. I'm not sure what's up with that, if it's a supply issue or just a hard "no" to anybody that isn't an OEM.

opencl5• 7 years ago

This article isn't about embedded SoCs? It's about desktop CPUs that are readily available at retail. Embedded SoCs are a pain to buy from most vendors except the Chinese ones you can find on Alibaba.

nottorp3• 7 years ago

Now... when will AMD fix power consumption on their video cards as well?

nottorp3• 7 years ago

Funny about those downvotes.

AMD can deliver 8C/16T in 65 W but their GPUs need 50%+ more power than nvidia's for the same performance (up to 100% more at the 1080 lower end). You're saying I'm not right and they don't have a problem?

dave7• 7 years ago

At this same event they also announced their 1st gen RDNA GPUs, called Navi. Also releasing to retail on July 7th. They supposedly go quite some way to reducing the gulf in GPU power usage/performance.

netrikare• 7 years ago

Does anyone know if AMD is working on supporting transactional memory in their cpus?

https://en.wikipedia.org/wiki/Advanced_Synchronization_Facil...

sorenjan• 7 years ago

How does new instructions, register renaming, etc work with different compilers? Say I'm using Visual Studio to compile C++, will it take advantage of the new processor features by default? What about if the binary runs on a different CPU, will the compiler include feature checks and multiple code versions?

horyzen2• 7 years ago

Not sure about VC++, but in gcc you can use -march=native to let the compiler compile the code with all instruction sets available on your CPU, I think there is a VC++ equivalent.

As for already compiled binary, depending on how it was compiled it may or may not work of a different CPU. Also the compiler doesn't do the runtime checks.

jjuhl• 7 years ago

GCC can do Function Multi Versioning (https://gcc.gnu.org/wiki/FunctionMultiVersioning , https://lwn.net/Articles/691932/) where it will generate code for multiple CPUs and select the best at run time.

ken• 7 years ago

AIUI, register renaming is a runtime feature of the microcode and has nothing to do with the machine language interface.

mhh__• 7 years ago

Correct. The compiler can be trained to utilise it efficiently but it's not a exposed feature

opencl5• 7 years ago

GCC and LLVM have supported multiple code versions based on feature detection for a few years, they call it function multiversioning. As far as I'm aware MSVC does not have this yet.

wahern2• 7 years ago

GCC has supported it for over 6 years, since 4.8. It was only added to clang in 7.0, released 8 months ago.

fulafel• 7 years ago

"new instructions" and "register renaming" are on opposite sides of the spectrum. It's up to your compiler to carch up with insn set additions, but register renaming is invisible.

holy_city• 7 years ago

RE new instructions, those appear to be mostly useful for things running on bare metal (like the OS kernel).

The under the hood stuff like true 256 bit registers, branch prediction, cache, etc, all is below the machine code level as other people have pointed out. The compiler doesn't know about it.

What about if the binary runs on a different CPU, will the compiler include feature checks and multiple code versions?

This is referred to as multiple/dynamic code paths and it needs to be supported by the processor microarchitecture and compiler. afaik only the Intel Compiler and Intel processors support it with the <code>-ax</code> compilation flag.

In general you should pick a minimum architecture for your applications, since it will be forward compatible.

choudanu4• 7 years ago

AMD’s primary advertised improvement here is the use of a TAGE predictor, although it is only used for non-L1 fetches. This might not sound too impressive: AMD is still using a hashed perceptron prefetch engine for L1 fetches, which is going to be as many fetches as possible, but the TAGE L2 branch predictor uses additional tagging to enable longer branch histories for better prediction pathways. This becomes more important for the L2 prefetches and beyond, with the hashed perceptron preferred for short prefetches in the L1 based on power.

I found this paragraph confusing, is it talking about data prefetchers (Which would make sense b/c of the mention of short prefetches) or branch predictors? (Which would make sense b/c of the mention of TAGE and Perceptron)

derefr• 7 years ago

A little of both. My understanding of the above paragraph is that the L1 predictor is trying to predict which code-containing cache lines need to stay loaded in L1, and which can be released to L2, by determining which branches from L1 cache-lines to L1 cache-lines are likely to be taken in the near future. Since L1 cache lines are so small, the types of jumps that can even be analyzed successfully have very short jump distances—i.e. either jumps within the same code cache-line, or to its immediate neighbours. The L1 predictor doesn’t bother to guess the behaviour of jumps that would move the code-pointer more than one full cache-line in distance.

Or, to put that another way, this reads to me like the probabilistic equivalent of a compiler doing dead code elimination on unconnected basic blocks. The L1 predictor is marking L1 cache lines as “dead” (i.e. LRU) when no recently-visited L1 cache line branch-predicts into them.

BeeOnRope• 7 years ago

I was also confused by this, but my reading is this is entirely about branch prediction nothing about caching. In that context L1 and L2 simply refer to "first" and "second" level branch prediction strategies, and are not related to the L1 and L2 cache (in the same way that L1 and L2 BTB and L1 and L2 TLB are not related to L1 and L2 cache).

The way this works is there a fast predictor (L1) that can make a prediction every cycle, or at worst every two cycles, which initially steers the front end. At the same time, the slow (L2) predictor is also working on a prediction, but it takes longer: either throughput limit (e.g., one prediction every 4 cycles) or with a long latency (e.g., takes 4 cycles from the last update to make a new one). If the slow predictor ends up disagreeing with the fast one, the front end if "re-steered", i.e., repointed to the new path predicted by the slow predictor.

This happens only in a few cycles so it is much better than a branch misprediction: the new instructions haven't started executing yet, so it is possible the bubble is entirely hidden, especially if IPC isn't close to the max (as it usually is not).

Just a guess though - performance counter events indicate that Intel may use a similar fast/slow mechanism.

sfink• 7 years ago

That was a great article. I wonder if fixing the reliability of their performance counters to work with rr ( https://rr-project.org/ ) is anywhere on their radar.

Sadly, until that happens, AMD CPUs are dead to me. For a C++ (or C or Rust) developer, rr is just too much of a productivity boost to give up.

BuckRogers2• 7 years ago

I bought the Ryzen 1700, 1800X and 2700X. Looking to upgrade to one of these, but will wait for benchmarks, AMD is really on a roll. The 3950X is extremely tempting especially considering I can drop it right in my existing AM4 motherboard. Allowing backwards compatibility where possible was the best move they made. I would've bought 1 CPU from them instead of 3 (and soon 4, and then 5 with Zen3), without it.

simplyinfinity• 7 years ago

zen3 would most likely be on a new socket, AFAIK. Zen2+ (4xxx series) would most likely be the last cpu for AM4, as amd have stated they will keep sockets for 4 years but that's OK since intel change it about every year or so.. I myself will be upgrading from 1700X to Either the new 8 core... but the 16 core looks so sweet...

BuckRogers2• 7 years ago

AMD's slides showed Zen3 as the next release (Ryzen 4000 series), as 7nm+/Zen3 in 2020. Zen2+ isn't a thing, unless AMD is simply calling it Zen3. I'm not sure the names matter, as Zen+ was better than I was expecting with the XFR2 changes, so I bought one. From what I can tell, they tied support to DDR4 support. I'm expecting Zen3 next year to be the last AM4 CPU.

Doesn't really matter to me, with the value they've been delivering since the original Ryzen launch, I see no reason to not buy them all. People appreciate a good discount on a desirable CPU on Craigslist when its time to upgrade. It's just an easy swap, especially if you use an IC Graphite thermal pad instead of thermal paste.

caycep• 7 years ago

I wonder if I'm misinterpreting TDP.

For the 105W TDP chip vs. say the 65 W one. If there is a lesser task not saturating the cores, the power/heat generation would be similar, and the bigger chip doesn't really ramp up the heat/wattage unless heavier loads are thrown at it?

dsr_• 7 years ago

For sibling chips like this, yes. Two cores being run at 90% utilization each will draw about the same amount of power regardless of whether you bought the 6-core version or the 8-core version.

Similarly, 4 cores running on the 12 or 16 core chips should eat about the same amount of power as each other.

AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome

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