TSMC Kicks Off Volume Production of 7nm Chips

https://www.anandtech.com/show/12677/tsmc-kicks-off-volume-production-of-7nm-chips

by dbcooper • 8 years ago

237 102 8 years ago

anandtech.com

shepting• 8 years ago

It's just stunning how they have been able to achieve 7nm features. With a 193nm wavelength laser no less.

dbcooper2• 8 years ago

7nm is really just a node name. Gate length is probably about 20nm. Still very impressive though!

dogma11382• 8 years ago

The gate pitch is 54mm for TSMC and 56nm for Global Foundries @ 7nm.

AnimalMuppet• 8 years ago

Well... the article didn't say what the line width, say, actually is. It just said that the process is labeled 7nm, which doesn't necessarily correspond to any features actually being 7nm in size. It just means it's that much smaller than the previous process.

Don't get me wrong, it's still amazing, and the line widths are still going to be much less than 193 nm. I just wish they'd say what some standard feature size actually is.

dogma11382• 8 years ago

It’s not 7nm in any feature size it’s seceral times that.

It’s achievable usually with multiple patterning and submersion 193nm wavelength in vacuum which goes to about 145 in water and they likely are using something other than water and you also have temperature which affects the refractive index.

awalton4• 8 years ago

Yeah, you should take the fact they're not using EUV as the tremendous boulder of salt that it is: these are actually 10nm parts. Node names continue to be washed into Megahertz War-style naming schemes.

TSMC's process lines up pretty well with Intel's published numbers for their P1274 10nm process (Contacted Gate Pitch T & I: 54 nm, Minimum Metal Pitch T: 40nm I: 36 nm, High-Density SRAM bitcell size T: 0.027 µm^2 I: 0.0312 µm^2, etc).

What we've learned out of all of this is that Intel's struggles to push tooling towards EUV have benefited the industry at wide, as everyone's spent so much effort there that existing processes and tooling has become cheaper and faster to iterate. They've certainly fallen behind their all-time lead of almost two process generations, but they still appear to be about a generation (18-ish months) ahead of TSMC by published numbers.

But, who actually cares about the numbers, Marketing says 7nm so it's 7nm.

Already__Taken• 8 years ago

There's a big difference when you compare making 7nm features with about 100 process steps whereas EUV are doing it in like 4 steps.

deepnotderp• 8 years ago

1. Not really 7nm, only the fin width is ~7nm, metals, etc are more like 54nm.

2. Immersion lithography (water as refractive index) + multiple patterning + computational lithography.

vardump• 8 years ago

I wonder how reliable and durable 7nm chips will be. We might start to see chip failures even after a few years of use.

https://semiengineering.com/transistor-aging-intensifies-10n...

FPGAhacker2• 8 years ago

Good question. Node size used to have a pretty firm definition, but it's malleable these days.

Regardless of the absolute number, you can think of it as defining the smallest width of pencil you are used to make a drawing with. You can still use fatter pencils, and in many cases you would want to... shading in a large area for example. But having the smaller pencil lets you put in finer details.

Some thing just won't work if they are too small though, so even though you have a fine sharp pencil available to use, somethings will not change.

Regarding reliability over time, electromigration is the only thing I know of in a typical IC that causes degradation. It is affected by the size of conductors, so potentially things could get worse. It's a well understood phenomenon though so it's usually mitigated by design rules.

Non volatile memories have their own degradation problems.

Lind5• 8 years ago

There's no shortage of issues https://semiengineering.com/unsolved-litho-issues-at-7nm/ https://semiengineering.com/chip-aging-accelerates/

rb8083• 8 years ago

Wow. I still remember being amazed when micron widths came out. 7nm is close to a miracle.

Semiconductor manufacturing improvements like this really have enabled the whole tech world improvements of the last few decades.

digi_owl• 8 years ago

In a sense it has been the "free lunch" of the industry, much like stored energy in hydrocarbons has been for manufacturing in general.

But the supposed exponential curve that stock markets loves to salivate about seems to once again turn into an S curve.

burnte• 8 years ago

There isn't any feature of the transistors taht are 7nm wide, the smallest feature IIRC is the interconnect, which is about 30n-40nm. "7nm" is marketing wankery. https://en.wikichip.org/wiki/7_nm_lithography_process

rb8083• 8 years ago

Thanks, kinda ruined my day but I learned something.

Havoc• 8 years ago

Well that's annoying. How is anyone supposed to judge anything if they just make numbers up?

FPGAhacker2• 8 years ago

Not quite accurate. There are a number of dimensions involved. Interconnect is definitely not the smallest.

This article show some examples: https://www.semiwiki.com/forum/content/3046-new-frontiers-sc...

fspeech• 8 years ago

If you look at the SRAM bit cells, they halved in area from 28nm to 14nm, and halved again from 14nm to 7nm. This is likely due to metal interconnects or other features only halving in spacing going from 28nm process to 7nm. So the scaling almost appears to apply to only one dimension (full linear scaling of two dimensions would have quartered the cell area at each step resulting in a 16-fold total reduction). But it is still scaling nevertheless.

typon• 8 years ago

There are different features sizes in the Z direction and different feature sizes in the XY plane. When it comes to XY, the smallest features size is probably the gate length. When it comes to Z, the gate oxide width is probably the smallest at 1-2nm. We have something called atomic layer deposition which gives control over single atomic layer thicknesses.

CamperBob23• 8 years ago

I've always assumed that "XX nm" doesn't represent the geometry of any particular feature of the end product, but something related to the wavelength of the radiation used for the imaging process.

Maybe it corresponds to the principle emission line of the light source (synchrotron?) In spectral terms, 7 nm is near the border between hard UV radiation and soft X-rays.

agumonkey• 8 years ago

This talk host said he doesn't believe 5nm will crack (unless major electronics breakthrough)

https://www.youtube.com/watch?v=JpgV6rCn5-g&t=1136s

manaxi• 8 years ago

Semiconductor manufacturing improvements like this really have enabled the whole tech world improvements of the last few decades.

I would argue that for software it had the opposite effect, and has led to layers upon layers of crap. No need to ever fix that when you can rely on the next cpu being twice as fast.

hexane360• 8 years ago

Don't forget that optimization also costs time. Performance improvements just shifted the equilibrium between optimization and output. In the world where every programmer was forced to optimize their code, we'd have a lot less code.

jannes• 8 years ago

Did any chip vendor announce 7nm chips yet? Or is this still secret?

tux3• 8 years ago

AMD's Zen2, which should come in or around 2019, will be on GloFo's 7nm.

I believe TSMC will use 7nm for some memory and mobile applications.

As for Intel their largely accepted equivalent to other foundries' 7nm is their 10nm, which is introduced in Cannon Lake/Ice Lake.

tim333• 8 years ago

Also "Apple's 'A12' chip reportedly in production using 7nm"... "destined for 2018 iPhone models."

mappu• 8 years ago

It's widely reported that the Snapdragon 855 will be on 7nm.

srcmap• 8 years ago

There a quite a bit of them already - just google it:

https://www.google.com/search?q=7nm+tapeout+press+release&cl...

AMD, GPU, FPGA, etc.

nullnilvoid• 8 years ago

Interesting time. This is the first time TSMC leads Intel in terms of node features if I remember correctly.

bigtones• 8 years ago

I have a question - why does the fab machine lithographic printing etch out a half a chip on the edge of the wafer like in the article picture. I presume the wafers are a standard 300mm size, so is it just because the designers were too lazy to remove the half chips on the edges from their mask template designs ?

rb8083• 8 years ago

Aha I had a question too why wafers are round. The answer is Crystals form in a cylinder then sliced. https://en.wikipedia.org/wiki/Wafer_(electronics)#Formation. Sorry it doesn't answer your question but helped me. :)

tropo3• 8 years ago

You could slice a cylinder the other way. That would give you rectangles, with the short dimension varying. I'm not so sure you'd save any space, but recycling the unused portion might be more reasonable to do.

chas• 8 years ago

It makes it so all of the chips they will use have all of their neighbors, so the process (and thus electrical properties) will be more uniform between chips near the edge and chips near the center.

pocak• 8 years ago

If your chips aren't very large, you can fit multiple copies in the reticle. E.g., if the litho machine has a 40mm by 50mm reticle, and you're making a 10mm by 10mm die, you can expose 20 dice at a time. It's usually worth it to go out to the edges even if you only get a few complete chips from the exposure. I can't find a wafer picture for Nvidia's GV100, but presumably a giant chip like that uses the whole reticle, so I don't expect to see partial chips on its wafer.

nl2• 8 years ago

Note that the TSMC 7nm process is similar in feature size to Intel 10nm.

https://en.m.wikipedia.org/wiki/7_nanometer#7_nm_process_nod...

craftyguy• 8 years ago

Strange that there's no citation for that claim.. do you have one?

nl2• 8 years ago

Here’s a comparison of the GF 7nm and Intel 10nm. It’s the same for TSMC afaik https://www.semiwiki.com/forum/content/7191-iedm-2017-intel-...

developer12• 8 years ago

Both Transistor Gate Pitch (nm) and Interconnect pitch (nm) are same or smaller for Intel's 10nm process compared to TSMC.

https://en.wikipedia.org/wiki/10_nanometer

sambull• 8 years ago

Looks like Intel isn't having much luck there.

ChuckMcM2• 8 years ago

Fun stuff. I've got a key chain with an 80186 die, and a couple of the binders from Microprocessor Forum when they had dies on the cover. The features on those chips are "huge" compared to these things. I suspect a die using one of these processes that was big enough (say 100 sq mm) would just look like a mirror with chromatic interference lines running across it.

This announcement also bookends nicely with the first home made IC one (https://hackaday.com/2018/04/24/first-lithographically-produ...)

opencl2• 8 years ago

ICs have just looked like mirrors for a while now.

See this shot of a 14nm Vega die on the left and 28nm Fury die on the right: https://www.techpowerup.com/reviews/AMD/Radeon_RX_Vega_Previ...

loser777• 8 years ago

I think you linked to a flip chip---you would expect a mirror finish from the bulk silicon side.

bhouston• 8 years ago

10nm wafer, sort of looks like a mirror: https://www.notebookcheck.net/fileadmin/Notebooks/News/_nc2/... Another: https://www.tweaktown.com/news/54490/samsung-10nm-finfet-soc... And an Intel ARM: https://techreport.com/r.x/2017_09_20_Intel_shows_off_proces...

Taniwha• 8 years ago

when we went above ~3 metal layers upper layers started to be used power and ground planes - that tends to mean that you can't really see much any more

ChuckMcM2• 8 years ago

I hadn't thought of that. It will make the chip decapping people sad as well because you really need xrays to see through the metal layers.

madengr2• 8 years ago

I have an IBM pin with a 1 Mbit chip. It was a big deal in the 80’s

bitL• 8 years ago

I assume the production is already sold out for the next year for Bitcoin/Ethereum miner ASICs...

I am wondering for how long will we be stuck with 7mm/10mm (Intel) tech; maybe we will see the last silicon-based improvements in CPUs & GPUs for the next two decades...

arbie• 8 years ago

ASICs usually trail leading edge nodes by several years.

tfha3• 8 years ago

According to what evidence? Due to yeild tolerance, they tend to be among the first made, even getting made during risk production.

ttul• 8 years ago

Deep into science fiction here with EUV...

hardwaresofton2• 8 years ago

So one of the most important questions when producing >10nm process is yield. In the article I can't really find yield numbers, and the only thing they mention is the SRAM chips getting "consistent double digits" -- so pessimistically consistently 10% yield. That's not "good" yield.

Also, IIRC SRAMs are just about the simplest blocks you can make, which means they're the simplest lithography wise. Simple blocks to make, so they're usually good candidates for exploration of new process...

7nm is hard (I've said in a previous post, but you're just fighting physics at that point, nevermind all the issues you start facing with crosstalk/etc), color me skeptical that they've really nailed down a "volume" process for doing it just yet.

calchris42• 8 years ago

Yields will suffer with current DUV process which must be multiple, multiple patterning. The mentioned switch to EUV reduces multiple patterning and should improve yield. But EUV has had its own challenges.

awalton4• 8 years ago

I can't really find yield numbers

This is not surprising - this is trade secret information as it directly translates to profit margin for the process. AFAIK nobody publishes process yield information other than vague handwavy percentages.

You should also expect percent yields of most processes these days to be pretty poor (numerically): each step brings its percent breakage along, so at 100+ steps for these current processes, you're losing a significant fraction of chips. (Even if all of your steps yield 99%, you're down to 36.6% yield after 100 steps, so it's really important to reduce the number of steps as well as their complexity.)

For a process to be profitable it doesn't need to have a perfect, or even "good" yield though (and so-called "perfect wafers" have been vanishingly rare since about the 14nm process step). I've read documentation about very old processes with yields of 60% that were considered "good" at the time, so 10% might not be a terrible overall yield at this process node (e.g. if we take our 36.6% yield example above, 10% total yield would be of 27% of theoretical - certainly room for improvement, but better than many pharmaceutical processes).

This underlines the importance for the switch to EUV - a dozen or more DUV multi-patterning steps can be dropped down to a single EUV step, which eliminates losses along those multi-patterning steps.

mud_dauber• 8 years ago

Agreed. About the only number I'd expect from a foundry is a defect density per unit area, which can be used to derive a yield estimate. It's die-size and design-quality dependent, so the quoted D0 is going to be a best case.

10% most certainly is a terrible yield. If TSMC is kicking off volume production, then they have a mostly-SRAM test vehicle somewhere, probably 288Mb or larger, yielding at 65 pct or better on a consistent basis. A 10% wafer would be a financial disaster.

gok• 8 years ago

I think you mean <10 nm?

hardwaresofton2• 8 years ago

Good catch, I definitely meant to write <10nm but I guess it also applies to >10nm too, basically it always applies. Doesn't matter if you can make Xnm process if it's not mass producable (unless your market is specialty chips of course)

ksec• 8 years ago

Does it matter though? What matter is cost, because that is the results of yield and direct relate to how many customers will use 7nm. Yield is not a constant and changes / improves over time.

60% Chance Apple will have a new iPad Pro in WWDC using 7nm, and 90% Chance Apple will use 7nm in their next iPhone.

Whatever the yield is, it is good enough for ~200M iPhone next year and the cost is acceptable for close to 50 customers in the next few months. And assuming Apple is going to go 7nm ( I don't see why not ), this volume will likely be more than double Intel shipping their 10nm in the next 12 months.

fredch• 8 years ago

Wake me up when EUV's here...

ekr• 8 years ago

This makes me hope that maybe all those chipmakers will finally move on from that extremely long-lived 28nm node. It has been heavily used since 2011-2012 and even companies like Qualcomm have been using it as recently as last year in the lower-end range of products. Companies like Allwinner, Rockchip, Amlogic have yet to release a single chip on newer nodes.

What this means is that the 28nm node has been the cheapest now for 7 years running. Usually, when new nodes came up, the cost per transistor initially was lower, while the yields are slowly improving. But after ~1-2 years, the new node was always more cost-effective then older nodes, per-transistor.

This wasn't the case with the 28nm, which stuck around for 7 whole years, and still seems to be the most cost-effective. But surely, now with 7nm available that won't be the case for much longer. Good riddance.

phkahler• 8 years ago

28nm will be around for a long time. There are SoCs up at 130 or 180nm still because for what they need those are the cheapest way to go. 28 is as far as you go with planar transistors and single (or is it double?) patterning. The 20-22 node is not popular because it kinda sucks for both planar and FinFET designs. I think 14-16 will be around for a long time too because of the increased complexity of going lower.

While the end of scaling is a bummer, it will be nice to have the industry settle on a few common nodes that are mature and very well understood.

nickik• 8 years ago

Great. I hope Esperanto Technology can come out with their RISC-V chip soon.

TSMC Kicks Off Volume Production of 7nm Chips

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