Lind5

part 2 of this series https://semiengineering.com/rethinking-memory/

"In addition to increasing capacity and speed, the improvements in energy efficiency are noteworthy. With HBM3, the core voltage is 1.1V, compared to HBM2E’s 1.2V core voltage. HBM3 also reduces the I/O signaling to 400mV versus 1.2V for HBM2E. There will be further improvements in future generations, as well."

may even go to FP4 standard!

AI already has led to a rethinking of computer architectures, in which the conventional von Neumann structure is replaced by near-compute and at-memory floorplans. But novel layouts aren’t enough to achieve the power reductions and speed increases required for deep learning networks. The industry also is updating the standards for floating-point (FP) arithmetic. https://semiengineering.com/will-floating-point-8-solve-ai-m...

Astounding amount of semi investments. $500B in this list alone https://semiengineering.com/where-all-the-semiconductor-inve...

Software engineers looking for a job should consider the chip industry, which is not just about hardware engineers. Plenty of software engineer openings https://semiengineering.com/jobs/ and many are remote

this related article addresses some of the cost issues https://semiengineering.com/designing-ics-in-an-increasingly...

Dealing with the exponential increase in data is driving some massive architectural changes. This Univ of Penn research is interesting. Chip companies are currently working a number of strategies. Related: https://semiengineering.com/ic-architectures-shift-as-oems-n...

not just the chip shortage. The rise of RISC-V coincides with a couple of other events in the industry. The first is the slowing of Moore’s Law, meaning that increases in total processing power no longer comes along with each new fabrication node. The second is the meteoric rise in machine learning, demanding massive increases in processing power. https://semiengineering.com/why-risc-v-is-succeeding/

More info here from the discoverers at ETH Zurich https://comsec.ethz.ch/research/microarch/retbleed/ and here is the actual technical paper https://comsec.ethz.ch/wp-content/files/retbleed_sec22.pdf

Semiconductor Engineering does a monthly startup funding report. All are chip industry related

https://semiengineering.com/knowledge_centers/startups/

Hybrid bonding big part of this https://semiengineering.com/hybrid-bonding-moves-into-the-fa...

Intel’s support for RISC-V marks a technological and cultural shift https://semiengineering.com/which-processor-is-best/

also relevant & more recent https://semiengineering.com/reliability-concerns-shift-left-...

title was too long. Here it is "A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses"

"The practice of “zero trust” is particularly important here. Any device or software outside the organization cannot be trusted". Great approach but it is amazing how many breaches are still happening due to lack of basic prevention measures taken

Gamechanger in automotive? “These compelling benefits are leading to mass SiC adoption in BEVs, which brings SiC manufacturing cost reductions due to economies of scale”

"as more autonomy is added into vehicles, the latency of a centralized gateway is proving unworkable. Tighter interdependence, scalability, and flexibility are all required, which a zonal architecture allows, and OEMs are at varying stages of adopting this approach. Strikingly, the automotive zonal architectures look a lot like scaled-down HPC data centers."

Copyright violation of Semiconductor Engineering https://semiengineering.com/breaking-the-2nm-barrier/

Questions about authenticity can occur at a supplier, with contractors to a supplier, or during the movement of components between contractors and to the customer. The types of anti-counterfeiting options to be used depend both on the value of the component and the consequences of fake components. But they all focus on the ability to uniquely identify a component so it can be tracked through final system assembly https://semiengineering.com/new-and-innovative-supply-chain-...

These terms tend to invite a lot of confusion. First of all, open source is not the same as free. In fact, the best open source hardware is a proprietary implementation of code that is maintained by the open-source community, and unless you have endless time and resources, you probably don't want to do this yourself. In chips, an open-source implementation typically involves a "free" instruction set architecture, and the hot one today is RISC-V. Others include MIPS and POWER, which are open-source, but you can't play with the source code like you can with RISC-V.

An SoC is a whole-different beast, because it contains all of the other things needed to create a system, including on-chip memory, I/O, interconnects, possibly some analog components, and it all has to work together. The more complex ones have multiple power domains, circuits that turn off when others turn on, and there needs to be embedded software in some of these devices. Depending upon what process node it was developed at, it also may require multiple voltages and a complex power delivery network. And if you really want to push the performance, you probably want to put this into a complex package, possibly including other chips. Having configurability in there in the form of an FPGA or some programmable logic is an interesting option, which is what Intel has done and presumably what AMD will do with its proposed acquisition of Xilinx. That helps keep it tuned to changes in algorithms for AI and machine learning without having to completely re-do the design.

The challenge will be finding design tools to make sure you haven't messed up anywhere. The free tools tend to be difficult to use and generally ineffective. The commercial tools are much better, but they're also expensive. And the more complicated the design, the more you'll probably need to buy some expensive hardware or lease it from the cloud. Programmability won't solve any of this. It will simply help avoid obsolescence, or at least slow it down.

There's a good article on open source here: https://semiengineering.com/riding-the-risc-v-wave/, with more links at the bottom if you need more.

note, that there are tradeoffs in performance & power when you add all the security measures you want https://semiengineering.com/security-tradeoffs-in-chips-and-...

Better approaches to deal with counterfeiting issues are emerging https://semiengineering.com/new-and-innovative-supply-chain-...

There are a number of full-3D designs in the works today. The challenge has been thermal dissipation, and as long as it's not logic-on-logic, it works. So that becomes a placement challenge, and EDA tools are still catching up. But there are some interesting new approaches out there, too. TSMC has figured out a way to stack chiplets inside a chip. So rather than going up, it's going down. They say that approach solves the thermal issues because the silicon acts as a heat sink. Here's a story that explains it: https://semiengineering.com/momentum-builds-for-advanced-pac... (Scroll down to the SoIC stuff under TSMC). The front-end packaging is new, meaning it's done at the front end of the manufacturing process. More work is being done the traditional way, too, whether it's pillars rising up off a substrate, or die on die (or die on die on die).

Arm’s primary base is in the IoT and the edge, and it has been very successful there. Its focus on low power allowed it to shut out Intel from the mobile phone market, and from there it has been gaining ground in a slew of vertical markets ranging from medical devices to Apple computers. But as more intelligence is added to the edge, the next big challenge is to be able to radically improve performance and further reduce power, and the only way to make that happen is to more tightly customize the algorithms to the hardware, and vice versa https://semiengineering.com/nvidia-to-buy-arm-for-40b/

This may be useful https://semiengineering.com/knowledge_centers/communications...

per the article:

-SMIC is shipping 14nm finFETs, with a 7nm-like process in R&D. -Yangtze Memory Technologies (YMTC) recently entered the 3D NAND market with a 64-layer device. A 128-layer technology is in R&D. -ChangXin Memory Technology (CXMT) is shipping its first product, a 19nm DRAM line. -China is expanding into compound semis, including gallium nitride (GaN) and silicon carbide (SiC). -China’s OSATs are developing more advanced packages.

Several foundries are ramping up their new 5nm processes in the market, but now customers must decide whether to design their next chips around the current transistor type or move to a different one at 3nm and beyond https://semiengineering.com/5-3nm-wars-begin/

There are big shifts in the economics of security technology https://semiengineering.com/fundamental-changes-in-economics.... More and higher value data, thinner chips and a shifting customer base are forcing long-overdue changes in semiconductor security

please check out listings here as they might be a fit for your experience https://semiengineering.com/jobs/