RISC creator is pushing open source chips

http://gigaom.com/2014/08/19/risc-creator-is-pushing-open-source-chips-for-cloud-computing-and-the-internet-of-things/

by Tsiolkovsky • 12 years ago

175 93 12 years ago

Assuming Moore's Law is slowing down, and there's no rabbit about to be pulled out of a hat by Intel or others, it's going to close the gap significantly between what is possible on an $x billion and an $x million budget. This makes it a great time for initiatives such as this to take place.

In 2001, an unexpected delay of 18 months could mean that you release to competition running at 2ghz instead of 1ghz. These days, Intel's 32nm, 22nm chips (and 14nm, from what is known about Broadwell) are more or less identical from a consumer's perspective.

As an aside, Patterson's book (coauthored with Hennessey), Computer Architecture: A Quantitative Approach, is one of the best I've ever read. Right up there with SICP.

richardwhiuk• 12 years ago

Definitely agree about the quality of Hennessey and Patterson's Computer Architecture book.

I think the reason that the 32nm, 22nm and 14nm chips are identical from a consumer approach is because of two issues.

One is marketing - we no longer have convincing benchmarks that are as persuasive as the GHz a chip would support. It was a questionable metric anyway, but it now isn't being pursued (for a whole number of reasons).

The second is an application space problem - consumer applications are no longer exploiting CPU improvements in the same manner. That's partially because we now get more parallelism rather than single threaded speed, but it's partial a testament to the success of the previous generation as to the breadth of tasks a current PC will happily perform in a reasonable time frame.

pjmlp4• 12 years ago

Yes, the time to update the computer every three years to keep up with the progress is now gone.

Maybe when we finally get to quantum computers a similar cycle will happen, but to the dismay of OEMs the cycle is gone.

Even mobiles already reached the same peak and are mostly driven by contract renewals nowadays, not features.

darkmighty• 12 years ago

I think we're at a bridging moment. Most computing tasks we came up on the last decades which were very hard to get done are now trivial with some optimization. Yet the general purpose ("universal") algorithms we dreamed of are still not in reach -- it's easy to think of an evolutionary algo huge neural net to do AI, but in practice universality implies (still) inaccessible search spaces. So hrdware looks as if standing still.

userbinator2• 12 years ago

As someone who has watched the "RISC revolution" and the claims its proponents have been making since the 80s, I'm not so optimistic on what will happen. Initially it was all about increasing clock frequency to make up for increased instruction counts and decreased code density, but Intel's Netburst showed that this strategy was a dead end. Then the focus was on power efficiency, which is still a close battle today. I don't think it's a matter of budget; AMD has much less to spend than Intel, yet it makes x86 CPUs that are still quite competitive even if they're not as fast - the gap between them is nowhere near their differences in budget. It seems that things are more like "fast, cheap, power-efficient: pick two".

This related paper is an interesting read: http://research.cs.wisc.edu/vertical/papers/2013/isa-power-s...

I think x86 still has plenty of room for optimisation, and Intel are just doing it slowly according to market conditions. An open-source x86 core would be great - in fact, pre-MMX-level x86 is fully open, as all the patents on that have expired now.

pjmlp4• 12 years ago

I also lived through it, but I would say that RISC won in the end, just not exactly as its proponents thought.

x86 are no longer real CISC, as they moved the internal architecture to RISC, starting with the Pentium 4.

And all the other processors that matter are also RISC.

The real loosers were the VLIW proponents.

rbanffy• 12 years ago

In order to be as efficient as a more naïve RISC architecture, x86 has to be very optimized with an Intel-sized budget behind it. For a RISC core to be as performant as a modern x86, it has to become much more complex (and it starts to resemble an x86 core, without the x86 decoder in front of it).

solarexplorer• 12 years ago

I think the point is not so much that RISC-V is better than x86 or that RISC-V with the same budget would be better than x86, etc. The point is that since RISC-V so simple, that you can produce _your_own_ customized cpus with a very small budget. Like adding special instructions, a special memory hierarchy, a special on-chip-network, whatever. It certainly made sense for digital signal processing, graphics and networking. It may make sense for other domains too.

These custom chips have the potential to be much more power efficient (for their special class of applications) than off-the-shelf general purpose chips.

With RISC-V it will be easier to start your own CPU design...

DCKing2• 12 years ago

Well there's two predictions you can think about that could happen sometime in the future:

1. Nobody can put more than XXX transistors on a square millimeter (where XXX is some physical limit to chip material)

2. "Everybody" can put YYY transistors on a square millimeter (where YYY is a number sufficiently close to XXX so that the difference does not matter much)

The first means some stagnation in the chip market: not only does Moore's Law not apply anymore, but not even does a weak version of Moore's Law ("chips tend to get faster/cheaper over time") apply. But if that scenario becomes true, it doesn't necessarily mean that the democratization of the second scenario becomes true. The ability to put YYY transistors on a square millimeter could still be limited to a select few companies investing billions in the production of these chips. After all, how many fabs worldwide are currently capable of producing 45nm chips, which could be considered "commodity" [1]?

Is it really true that it becomes much cheaper to produce chips on smaller process nodes over time? Sure it becomes cheaper since less original R&D is necessary, but is it reasonable to think that producing 20nm chips ever becomes a question of investing anything less than, say, 100s of millions? Does the second scenario ever become true, at least in the forseeable future?

I don't know much about chip fabs so I wonder if someone more knowledgeable could share some insight on this.

[1]: I genuinely don't know the answer to this, but I don't suppose it's very widespread?

mechagodzilla2• 12 years ago

These days, Intel is an unusual model in that they own the whole 'stack', from processor design to fabrication, packaging, etc. To replicate that costs 10s of billions of dollars.

To get your own chip produced using a 'pure-play' fab (which, these days, basically means TSMC, and to a lesser extent Samsung and GloFo), however, is much cheaper. If you want a 20nm chip, you design your chip (basically the cost is just engineering effort + CAD tools..a few million $$), send it to TSMC (getting masks made is another few million $$), and they send you back chips.

Reality is slightly more complicated, in that you're using using an integrator to manage the relationship with TSMC, the packaging company, the testing company, etc., but a startup with $10-20 million could probably scrape together a decent 20nm chip.

Once TSMC has built a new fab though, the longer it is 'relevant' the cheaper they can make the wafers, as they have more wafers to amortize the ~$10 billion or whatever it cost to build the fab over.

Symmetry3• 12 years ago

If I were to bet on which fabs were able to get to the final process node for traditional silicon transistors, my money would probably be on Intel and TSMC, since they have the most volume on advanced processes and spend the most money on new fabs and process research. And TSMC is the biggest commodity fab.

The reason it becomes cheaper is that your development costs for both the process and the design get amortized over longer and longer periods. At the same time architecture becomes the only way that some chips can be faster than others.

Though I guess I should point out that progress in chip performance isn't the same as putting more transistors on a square millimeter. One aspect of this is that more economical silicon processes such as TSMC's are better at cramming more transistors into a square millimeter than Intel's, but Intel's transistors tend to have better drive current - all at a given process node. The other aspect is that ever increasing transistor leakage means that processors might get to an era when they can't afford to keep all their transistors lit up at the same time[1].

[1]http://hopefullyintersting.blogspot.com/2012/02/dark-silicon...

cben• 12 years ago

If 2 keeps not happenning — if producing custom ASICs remains expensive — it becomes increasingly attractive to produce cheap as-good-as-they-get FPGAs in massive quantities.

Ironically, FPGAs as endgame would be way more disruptive than an "ASICs to the people" endgame.

FPGA density, price/gate and power efficiency trail "native" hardware but constant factors of overhead but it should be possible to reduce the gap compared to now. More FPGA volume means better economies; the hardware architecture could be optimized further; most importantly IMHO the current design tools are heinously unfriendly and could benefit a lot from programmer attention (once programmers realize a more-or-finalized FPGA structure is the "new assembly" to optimize for).

I'm not sure if a constant factor of disadvantage would become very acceptable (because we'll drop the throw-faster-hardware-at-it mentality) or very unacceptable (because robots with FPGA brains always lose at high-frequency chess wrestling to robots with native brains).

stephencanon4• 12 years ago

These days, Intel's 32nm, 22nm chips (and 14nm, from what is known about Broadwell) are more or less identical from a consumer's perspective.

That’s a little bit of a stretch. 32nm was Westmere -> Sandybridge, which doubled FP throughput and L1 load bandwidth, among other changes. Haswell doubled FP throughput again, doubled integer SIMD throughput, and doubled L1 load and store bandwidth, among several other significant changes, and there’s also been a steady ~10% per generation improvement in generic IPC. Consumers don’t care about those numbers, but they do care about some of the operations they enable getting faster. (In fairness, this often lags the release of the processors by a year or two as SW re-optimization is required to take advantage of new features; the full benefit of the changes isn’t available to consumers until some time after the processors are released, by which time we’ve all forgotten just how slow our old hardware was.)

The energy footprint of those processors has shrunken considerably in the same time, which is a huge improvement for portables.

valarauca14• 12 years ago

The energy footprint of those processors has shrunken considerably in the same time, which is a huge improvement for portables.

Yes and no. The Westermere, Sandybridge, Ivybridge, Haskell, Devil Cannon's line isn't really targeted for the mobile market. The shinking power budget is caused by 2 things.

1) To stay competitive against 64bit ARM processors. Intel processors are barely used in mobile devices. But eventually ARM will attempt to transition into laptop/desktop/server and compete with Intel directly, this is where lower power comes into play.

2) Feature set. New features (functionality) on chip cost not just dye space, but cost power and heat. The heat and power are the far most critical issues.

The second issue is commedically addressed in, "The Cold Winter" a satirical document about hardware engineering.

"The idea of creating more and more cores ran into an issue. Most people don't use their computer simulating 4 nuclear explosions while rendering Avatar in 1080p. They use their computer for precisely 10 things, of which 6 of things involve pornography.

The other issue was the 600 core dub 'Hydra of Destiny' was so smart that its design document was the best chess player in the facility. The issue was it required its own dedicated coal fired plant, and would run so hot that it would melt its way into the earth's core." - The Cold Winter (paraphased)

valarauca14• 12 years ago

The energy footprint of those processors has shrunken considerably in the same time, which is a huge improvement for portables.

Yes and no. The Westermere, Sandybridge, Ivybridge, Haskell, Devil Cannon's line isn't really targeted for the mobile market. The shinking power budget is caused by 2 things.

2) Feature set. New features (functionality) on chip cost not just dye space, but cost power and heat. The heat and power are the far most critical issues.

If your interested in a slightly satirical look at modern hardware scaling I suggest you read The Slow Winter http://research.microsoft.com/en-us/people/mickens/theslowwi...

Symmetry3• 12 years ago

You'll find very few workloads where Haswells doubling of vector sizes actually doubles throughput. I mean, if you're working set is already in your level 1 data cache it will, since you won't be bandwidth constrained in that case and you won't have the wide vector unit on long enough that the chip will have to start power throttling. This is a situation that comes up sometimes, but you won't see your program accelerate by anything close to 100% overall.

asb2• 12 years ago

If you'd like to be paid to work on a fully open-source RISC-V SoC, we're hiring. See http://lowrisc.org

igravious2• 12 years ago

Talking about the RISC-V Instruction Set Architecture

http://riscv.org/

Why would you need 128bit addressing? Isn't 64bit address space plenty big? This isn't a "nobody'll need more than 640k scenario, right?"

https://gigaom2.files.wordpress.com/2014/08/requirements-tab...

unwind• 12 years ago

There's motivation in the relevant part (RV128I Base Integer Instruction Set), starting on page 81 of the 2.0 ISA specification (https://s3-us-west-1.amazonaws.com/riscv.org/riscv-spec-v2.0...).

A choice quote:

It is not clear when a flat address space larger than 64 bits will be required. At the time of writing, the fastest supercomputer in the world as measured by the Top500 benchmark had over 1 PB of DRAM, and would require over 50 bits of address space if all the DRAM resided in a single address space. Some warehouse-scale computers already contain even larger quantities of DRAM, and new dense solid-state non-volatile memories and fast interconnect technologies might drive a demand for even larger memory spaces. Exascale systems research is targeting 100 PB memory systems, which occupy 57 bits of address space. At historic rates of growth, it is possible that greater than 64 bits of address space might be required before 2030.

userbinator2• 12 years ago

if all the DRAM resided in a single address space

Key point, and that's a huge "if". All large systems are NUMA, and trying to treat that like a uniform address space will be absolutely horrible because of the extreme latencies that arise.

valarauca14• 12 years ago

With advent of memristor based memory it'll be possible today (at extremely high cost on the order of a medium nation's GDP) have on the orders of petabytes of what will functionally be RAM. Only ~6-7 tick/tock cycles are necessary for that to expand beyond the address space of 64bit addressing (~10^19).

igravious2• 12 years ago

How long is a tick/tock cycle? A few years? 3 * 7 = 21. So we'd need to prep for going beyond 64bit some time before 2035? Which chimes with the quote At historic rates of growth, it is possible that greater than 64 bits of address space might be required before 2030 that 'unwind' kindly gives in a sister comment.

Seems like good forward planning but a little premature, no? These features must come at some cost. Surely you could have a re-vamp sometime around 2025?

sp3322• 12 years ago

IPv6-based addressing? :)

chrisdew• 12 years ago

Clutching at straws here, but...

One use case for 128 bit addressing is for a single-address-space OS running on a cluster. http://en.wikipedia.org/wiki/Single_address_space_operating_...

Pointers can have 32 bits for the IP address of the hosting node and 64 bits for the address within the node, and 32 bits spare for various flags.

krylon• 12 years ago

I have no idea if this is technically feasible, but it sounds like a sweet idea!

Narishma• 12 years ago

From the article: "Popular chip architectures historically have been locked down behind strict licensing rules by companies such as Intel, ARM and IBM (although IBM has opened this up a bit for industry partners with its OpenPower foundation)."

IBM's new openness isn't really open at all. It's just what ARM has always been doing: they allow you to pay them a lot of money so you can use their ISA in your CPU.

PinguTS2• 12 years ago

Please explain: What would be the benefit of an open source chip?

At the end of the day, the chip is a physical thing that have to be produced by someone. As long as there is no 3D printer, which can build nano structures to makes chips, I can only implement it into a FPGA. The main FPGA providers are either Altera or Xilinx and both a very expansive. So they are good for prototyping or very low volume. But for anything beyond, I need a specific implementation. Okay, I could go to a foundry like Samsung (or other) and order according to my design. But, even that requires a very high volume in the millions to make it affordable and viable from a business perspective. Especially, if it is intended for the IoT market. On the other side, I can buy ARM Cortex M0 and Cortex M1 for cheap from NXP and other for less than $1. They are power full and power consumption is very low.

Just to mention, the other day the WRTnode[1] was released for less den $25 or look at an Raspberry PI Compute. Don't get me wrong, Yes, I would like to see those with an open source chip. But would that be really a viable business case, except from the University context?

[1] http://wrtnode.com/

sp3322• 12 years ago

I can buy ARM Cortex M0 and Cortex M1 for cheap from NXP and other for less than $1

So imagine how cheap these new CPUs could be!

FigBug• 12 years ago

Arm licensing fees are about 1% - 2%, so these new chips would be less than $0.98?

worklogin2• 12 years ago

What's the point of an open source operating system? Most people buy their computing device with the OS installed, so the cost is marginal.

PinguTS2• 12 years ago

You are not from the hardware business?

In hardware design you cannot build a "minimal viable product" and then do "continuous integration" from that on. A hardware product either works within its defined limits or it doesn't. Then, depending on your limitations, you need additional approval by FCC, FDA, and such organizations within the US alone. The same thing then with their counterparts in every different country. Chip design is then the next level up. Because changing a mask later on, because you found a bug, means you produced a million chips just for the dust bin.

That means the entry barrier into hardware, especially chips, is very high.

alricb2• 12 years ago

On reason that's mentioned in the article: paranoia. If the chip is open-source, you can at least theoretically audit its manufacturing to make sure no backdoor is being inserted.

Also, return to the taxpayer. To me, a publicly-funded verification of RISC-V would bring wider benefits than that of a proprietary ISA like ARM [1].

http://www.cl.cam.ac.uk/~acjf3/arm/

tormeh• 12 years ago

A startup can make a better chip that runs the same binaries without asking anyone for permission.

Symmetry3• 12 years ago

If you want to write a paper exploring some new computer architecture feature it's very nice to have a real chip with an actual existing toolchain to use as a starting point.

Zigurd• 12 years ago

This paper http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-14... pointed to in the article posted here, claims higher performance per Mhz and lower power consumption than ARM in table 2.

Still, that requires some chip maker to build a SoC around a RISC-V CPU that attains these efficiencies in the real world.

The paper makes these arguments for RISC-V:

• Greater innovation via free-market competition from many more designers, including open vs. proprietary implementations of the ISA.

• Shared open core designs, which would mean shorter time to market, lower cost from reuse, fewer errors given many more eyeballs3 , and transparency that would make it hard, for example, for government agencies to add secret trap doors.

• Processors becoming affordable for more devices, which helps expand the Internet of Things (IoTs), which could cost as little as $1

The first point is not very concrete. China has long had some of their own MIPS-based RISC CPU designs, and they are most likely to act on the transparency issue. That leaves super-cheap processors for IoT. ARM may be able to deliver pricing and value that's better than free.

And all this assumes very low friction in the form of, say, Android adding this ISA to the standard set of compilation targets for native code, and, to ART pre-compilation.

comatose_kid• 12 years ago

David gave a nice lecture on RAID over a decade ago when I was taking a computer architecture class at Stanford.

Perhaps the next edition of his textbook (bible for computer architecture) should use RISC-V, it would probably help as a learning aid and spread the gospel about RISC-V.

Of course, it's possible that the current edition of the text already does this.

alricb2• 12 years ago

Chicken, meet egg:

We did not include special instruction set support for over ow checks on integer arithmetic operations. Most popular programming languages do not support checks for integer overflow, partly because most architectures impose a signicant runtime penalty to check for overflow on integer arithmetic and partly because modulo arithmetic is sometimes the desired behavior. [1]

Please Regehr, don't hurt them. [2]

[1] Spec, section 2.4 https://s3-us-west-1.amazonaws.com/riscv.org/riscv-spec-v2.0...

[2] http://blog.regehr.org/archives/1154

tachyonbeam2• 12 years ago

I happen to be implementing my own JavaScript JIT compiler and I can tell you that SpiderMonkey, V8 and my compiler all perform a lot of overflow checks. This is because in JavaScript, all numbers are doubles, but JITs typically try to represent them as integers where possible, because integer operations have lower latency.

Scheme and Common Lisp also rely on overflow checks to optimize small integers as "fixnums" instead of always using arbitrary precision arithmetic. Not having hardware support for overflow checks would complicate the implementation of many dynamic languages, and reduce their performance significantly.

Not sure what this guy was thinking. It can't be that hard to implement some overflow flag you can branch on, I mean, adders basically produces that information for free, don't they? Seems like a poor design choice.

ajb• 12 years ago

Hmm; carry is free, not sure about overflow. But more generally, it's an extra output, for what would otherwise be one-output operations. Put it this way - if a lot of javascript operations could modify a piece of global state, that would be trivial on a trivial interpreter, but I bet it would add a lot of complexity to your JIT. Same goes for CPUs - no problem for simple implementations, but it would add complexity to an out-of-order or other clever microarchitecture.

hornetblack• 12 years ago

Mill architecture support it, by having multiple add instructions. add is wraparound add. addx returns a NaR^[1]. addw returns a double width value. As Mill stores integer size of registers these instructions apply to all integer sizes and vectors, without having separate instructions for each width (and vectors).

[1] NaR will propagate an error, but trigger an exception if it's stored or branched on.

renox• 12 years ago

Yes, in this day and age, making a new ISA worst than the MIPS ISA (which had TRAP on integer overflow) with regards to integer overflow behaviour is really annoying.

IMHO this is cost saving going too far..

I wish that the mill succeed instead, at least it brings new things regarding security!

TheMagicHorsey• 12 years ago

Is licensing an ARM core really a barrier in a business/community venture, once you take into account the enormous costs of just getting a fab to make your chip?

I feel like the fabbing cost is so high, that at that scale, the CPU license fee is really nothing.

Correct me if I am wrong. This is coming from the mind of someone who knows next to nothing about how hardware is really made.

aidenn04• 12 years ago

I think the bigger consideration is that the ARM IP is encumbered. You can't tweak it and publish the changes you made.

ksec• 12 years ago

Exactly my thoughts. Licensing the ARMv8 is cheap, getting it to fab is expensive. And the current trends goes more advance nodes will be more expensive. Hence the move to smaller node will no longer be as much about getting cheaper. Until 450mm wafer comes out, which still does not have a proper schedule.

krmboya• 12 years ago

Maybe a bit OT, but I've just started learning programming for MMIX, Donald Knuth's RISC computer. I've been wondering when, or if, it could one day be implemented in hardware.

niix• 12 years ago

Every time I hear "RISC Architecture" I think of the movie Hackers.

ChuckMcM• 12 years ago

Perhaps the most important contribution Linux has made to the world is that because of its impact, you can run an OS on nearly any instruction set architecture (ISA). That drops a pretty huge barrier in terms of getting to something from nothing. On RISC-V though, unless it was some sort of SoC (which most people won't build) I don't see the impact. But carrying that line a bit further ...

One of the challenges that Microchip has faced was that the affinity for C that the ATMega architecture had from rival Atmel meant it lost a few significant design wins (Arduino perhaps the most serious). They could use RISC-V to try to offset the Atmel SAM series. But other than that I don't see the motivation for folks to not use ARM, granted a full processor license would be expensive but if you are looking at volumes where that would be an advantage, it isn't that expensive.

RISC creator is pushing open source chips

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