NASA selects SiFive and makes RISC-V the go-to ecosystem for future missions

https://www.sifive.com/press/nasa-selects-sifive-and-makes-risc-v-the-go-to-ecosystem

by georgelyon • 4 years ago

792 187 4 years ago

The article (nor the product page for the X280) doesn't say whether these chips are radiation hardened, or whether NASA is now more comfortable with software solutions to the difficulties of reliable computation in space.

If the latter, that seems (to a layperson) quite exciting, since more local processing capabilities will hopefully lead to more efficient use of the very limited radio bandwidth these missions have available at such vast distances.

qbasic_forever• 4 years ago

The last mars rover and its drone run embedded Linux, the JWST runs javascript (not node.js though!). NASA is already working with much more powerful and capable software stacks.

deelowe3• 4 years ago

the JWST runs javascript

What?! I'd like to know more about this. Does it have GC? I just can't fathom that being the case...

tibbydudeza5• 4 years ago

The rover still uses the radiation hardened PowerPC (RAD750 circa 2001 = 301K per CPU) but the drone uses a Snapdragon 801 SoC - it was not considered mission critical so the team could use off the shelf hardware.

https://en.wikipedia.org/wiki/RAD750

ThinkBeat• 4 years ago

except that the more complexity you add and make available the more things can break and go wrong.

I imagine it is an interesting balancing act.

_joel2• 4 years ago

More over, Inginuity uses COTS altimeter from Sparkfun, it's still working!

lizknope2• 4 years ago

Where are you reading that?

The Perseverance rover uses the VxWorks real time OS from Wind River Systems and the same RAD750 PowerPC processor that NASA has been using for the last 20 years. The rover is designed to last and operate a long time.

The Ingenuity drone helicopter uses an off the shelf Qualcomm Snapdragon 801 and Linux. While NASA wants it to last a long time that was not part of its main design.

https://www.pcmag.com/news/linux-is-now-on-mars-thanks-to-na...

noselasd2• 4 years ago

Well almost. The Perseverance rover runs vxworks, like most if not all of its predecessors. Ingenuity (the drone/helicopter) does indeed run linux.

jpm_sd2• 4 years ago

SiFive is fabless. Looks like they will be collaborating with Microchip on actual production.

https://www.nasa.gov/press-release/nasa-awards-next-generati...

https://www.electronicdesign.com/technologies/embedded-revol...

mzs2• 4 years ago

I see Microchip doing nothing but ARM in this space and only SiFive folks quoted in their PR:

https://www.microchip.com/en-us/products/microcontrollers-an...

adgjlsfhk1• 4 years ago

In general, the design has gone towards have 3 to 5 redundant non-hardened computers with ECC that compare results and if one computer disagrees, restart it. Radiation hardening makes sense when computers cost tens of thousands, and weigh 10s of pounds, but now they are cheap, and only weigh a few grams.

duskwuff• 4 years ago

SiFive X280 is an IP core, not an IC. The design itself isn't inherently radiation-hard, but there's nothing preventing it from being manufactured on a radiation-hard process.

mmaunder• 4 years ago

And yes, having more onboard processing will lead to more pre-processing capabilities for data before it's sent/received via precious and limited DSN bandwidth. Could also allow for a low quality preview and selective-send mode of operation.

IshKebab• 4 years ago

There are definitely things you can change in the design to make it more radiation-proof. ECC memory for example, logic sanity checks etc.

noselasd2• 4 years ago

There certainly things you can do in the design to be radiation hardened, it's not just in the manufacturing. The LEON [1] processor, initally designed by ESA for space missions incorporates quite many countermeasures in its IP core.

[1] https://en.wikipedia.org/wiki/LEON

Someone• 4 years ago

Related NASA press release (I think): https://www.nasa.gov/press-release/nasa-awards-next-generati....

That seems to say it’s for a radiation-hardened design:

“In 2021, NASA solicited proposals for a trade study for an advanced radiation-hardened computing chip with the intention of selecting one vendor for development. This contract is part of NASA’s High-Performance Space Computing project”

They also say:

“The processor will enable spacecraft computers to perform calculations up to 100 times faster than today’s state-of-the-art space computers”

and

“Our current spaceflight computers were developed almost 30 years ago,”

That, for me, also points towards a radiation-hardened design. If it isn’t, 100 times faster than 30 years ago is an incredibly low hurdle to clear.

Also, it’s a $50 million firm-fixed-price contract. I have no idea whether that’s a sharp price for this, so can’t judge how much risk SiFive takes on with this.

lizknope2• 4 years ago

NASA currently uses the RAD750 which is based on a PowerPC 750 that was new in Macs in 1997.

https://en.wikipedia.org/wiki/RAD750

UltraViolence5• 4 years ago

The newer designs aren't actually RAD-hardened, but fault tolerant.

It's physically impossible to produce RAD-hard semiconductors at the small scale we're currently producing high-end CPU's with.

I read this in an article somewhere but don't have the link.

justahuman743• 4 years ago

I don't think SiFive is directly the contract holder, it'd be microchip who deals with nasa who obtained a cpu core from sifive

snvzz11• 4 years ago

100 times faster than 30 years ago is an incredibly low hurdle to clear.

"today’s state-of-the-art space computers" is not the same computer as "Our current spaceflight computers were developed almost 30 years ago".

tablespoon2• 4 years ago

The article (nor the product page for the X280) doesn't say whether these chips are radiation hardened, or whether NASA is now more comfortable with software solutions to the difficulties of reliable computation in space.
If the latter, that seems (to a layperson) quite exciting, since more local processing capabilities will hopefully lead to more efficient use of the very limited radio bandwidth these missions have available at such vast distances.

Is that either/or, though? I could imagine building a probe with a radiation hardened central processor (or two), plus a non-radiation hardened "accelerator" CPU that's not considered mission critical. The "accelerator" could be tasked with things like pre-transmission data analysis/triage, and if it fails the mission could continue without feature (like Galileo continued without its high-gain antenna).

Though the value of that might be less than it seems at first look: New Horizons had literal years of time to transmit its data back to Earth.

silasdavis2• 4 years ago

What is radiation hardening of chips?

Stuff on the outside to absorb? Different band gaps in the silicon?

Jtsummers3• 4 years ago

https://en.wikipedia.org/wiki/Radiation_hardening

Larger node, different substrate, shielding, and other things.

rawoke083600• 4 years ago

I always wondered can "you not just" dumped a your modern'ish pc in big bucket of mineral oil to fight of the radiation ? Given that water (and other hydrocarbons has been suggested as a shield material for cosmic radiation). As I understand It Cosmic Radiation is the bigger enemy than the "normal" beta/gamma radiation ?

inamberclad3• 4 years ago

I'm ready to throw our old, expensive, and fairly slow flight computers with no drivers and terrible lead time to the curb and get on board with something new. Especially if an open ISA means that our systems will be more portable and faster to develop.

smoldesu• 4 years ago

It really seems like the perfect storm. Hopefully other folks like NASA will get comfortable jumping on the RISC train now that their only option isn't licensing from ARM.

giantrobot4• 4 years ago

NASA's been on the RISC train for nearly 30 years. They've been using the RAD750 since the turn of the century. Before the RAD750 they used the RAD6000, a radiation hardened POWER1 chip. They also use the Mongoose rad hard MIPS chips in a number of orbiters.

gumby• 4 years ago

There are already companies building hardware and software stacks so you can concentrate on the part you care about. I think this is great!

Also excited to see RISC V gaining some acceptance in space.

SassyThrowaway2• 4 years ago

Especially if an open ISA means that our systems will be more portable and faster to develop.

So I understand that RISC-V does not immediately impose licensing fees, but how does that translate into portability and speed of development? I'd think that tools and toolchains do not especially benefit from there not being licensing fees, and do benefit from somebody paying cool kernel/compiler hackers. Tools hardware designers use as well as the designs themselves will stay closed. What am I missing?

tibbydudeza5• 4 years ago

Interestingly SiFive RISC V core was licensed by Tenstorrent (Jim Keller AI startup) for their designs.

FullyFunctional• 4 years ago

True but know also that Tenstorrent is working on their own superscalar OoO chip as well.

tibbydudeza5• 4 years ago

They probably need a "director" CPU with a familiar programming interface to orchestrate their AI engines ???.

neilv• 4 years ago

It's great to see parts of the US government embracing RISC-V and SiFive.

I hope NASA and others using RISC-V also take the opportunity, of a bit of a fresh start, to push for more of an open hardware platform around the CPUs (chipsets, devices, etc.).

1-6• 4 years ago

I hope that’s the intention. Silicon Valley pretty much sprouted with military funding. Unfortunately, projects with long lead times are impossible to sustain in this new economy and research scientists will get scouted before NASA gets to increase their pay.

gchadwick2• 4 years ago

I am a little surprised to see this. I'd imagine NASA would chose a CPU with an already proven track record (especially for something so wide ranging, the press release says it expected to be used for 'virtually every future space mission, from planetary exploration to lunar and Mars surface missions'. This is a new design from SiFive and there's not a huge amount of SiFive IP around yet to demonstrate how good (or otherwise) their verification is. Running into a hardware bug whilst your CPU is in space is not good.

Still good SiFive have convinced NASA otherwise, they must have a pretty strong verification story behind the scenes.

pinewurst4• 4 years ago

NASA is partitioned between the (IMHO limited) parts that actually do stuff and the golly-geewhiz-PR stuff. People who are planning next gen planetary missions are considering trusted, proven rad hard platforms. This is just PR to distract in its own small way from the SLS debacle.

permalac• 4 years ago

What debacle? Is it dead?

Jtsummers3• 4 years ago

This is just PR to distract in its own small way from the SLS debacle.

You're implying a degree of coordination which organizations the size of NASA just don't have. Artemis has had two scrubbed launches, they didn't put out this announcement to distract from it. I doubt someone went over to SiFive and said, "Hey, help us distract from the Artemis I launch problems and we'll give you a nice contract."

zitterbewegung• 4 years ago

The whole point of choosing SiFive over anything else is to encourage competition.

SpaceX is similar while they are very successful it also encourages competition in a space that really needed it and now there are so many other companies doing smaller launches that don’t make business sense to SpaceX.

omegalulw• 4 years ago

I absolutely love that NASA is doing this AND encouraging the RISC-V ecosystem. Maybe it's impossible, I don't know, but if we have an open soruce alternative for hardware with the kind of reach that Linux has in software i think that's the best way forward.

UltraViolence5• 4 years ago

I agree. NASA has hit the jackpot by using fixed-price contracts from vendors which don't have a legacy track record from the Apollo days.

The Cost-plus contracts have made them fat and lazy and somewhat remind me of that Bugs Bunny cartoon where the cats don't mind the mice emptying the fridge.

NASA is taking a small risk, but the rewards can, as SpaceX has demonstrated, be HUGE.

mlindner• 4 years ago

The alternative is the ancient PowerPC-based RAD series of which the most recent incarnation is now almost 2 decades old.

hajile• 4 years ago

SiFive is a new company (with backing from large companies like Qualcomm), but the people working there are industry experts with decades of experience who know the value of verification to both designers and customers.

dwrodri• 4 years ago

One of the main value adds of an open ISA + open reference implementations Chisel/Chipyard + access to RTL (I think?) is that LOTS of people are hungry for really good multi-core out-of-order CPU pipelines with super-stringent levels of provable correctness. I think the tooling ecosystem is on the right track in terms of providing a FOSS toolchain that supports this. It's not there yet, but you're average ECE master's student could probably teach themselves chipyard and start their own Rocket fork which is much easier to test/verify at the basic-block level than a lot of other tooling I've used.

brucehoult4• 4 years ago

Note that X280 is not OoO. It's the same proven dual-issue in-order U74 core (similar to ARM A55) what has been out for a few years, and is just now hitting Raspberry Pi levels of price in the VisionFive 2 and Pine64 Star64. The X280 just has an added RISC-V Vector unit.

whazor• 4 years ago

Also because the CPU layout is generated by software, maybe it is easier to add custom constraints specific for space.

morcheeba• 4 years ago

Interesting! ESA has been using a custom SPARC V8 rad hard architecture: https://en.wikipedia.org/wiki/LEON

I'm currently using a dual-core 90 MHz processor that is relatively advanced and has good performance for many applications. It has error-correcting memories (SDRAM, cache, registers) and a lot of integrated peripherals (spacewire, serial, ethernet, 1553, CCSDS) that help reduce board complexity.

Next up in the pipeline is an 8-core 1 GHz monster: https://www.gaisler.com/index.php/products/components/gr765

pkaye2• 4 years ago

NASA has mostly been using a PowerPC.

https://en.wikipedia.org/wiki/RAD750

shrubble• 4 years ago

Are any of these boards available for regular people at a regular person kind of price? Or is it 1000s of USD for an evaluation board?

techdragon2• 4 years ago

It’s super hard to get pricing info for radiation hardened chips that are currently being sold, let alone just buying one from Digi-Key. It’s pretty damn annoying if you just want the one super robust chip for a system supervisor or something else like that, to have no idea how to plan the design for a cost budget before you begin doing a lot of contact work talking to people for price quotes. It’s a weird ecosystem that feels surprising antiquated compared to the more modern parts of the embedded ecosystem that I’m familiar with.

Worst price I can remember off hand was $15 grand USD for a radiation hardened microcontroller, pretty sure it was an Arduino mega family chip I could have gotten the industrial quality version of for $25 bucks from Digi-Key… if I didn’t want it radiation hardened.

myself248• 4 years ago

Interestingly enough, the LEONv3 architecture also underlies the SkyTraq Venus8 GPS/GNSS chips, which are in the Navspark arduino-compatible modules, which means there's a really, really accessible toolchain for 'em. Just add the board support URL to the IDE, and voila, you're building for LEON.

The NavSpark Mini is still $36 for a 6-pack, making it one of the cheapest uCs with a floating-point unit. (The ESP32 technically has one, but its performance is inexplicably poor.)

I'm not clear on whether SkyTraq's chips have all the error-correcting goodies that're in other LEON implementations; would those be baked in by default?

skissane2• 4 years ago

Interesting! ESA has been using a custom SPARC V8 rad hard architecture: https://en.wikipedia.org/wiki/LEON

While LEON isn't going away any time soon (especially given the recent release of the new LEON-5), I very much get the impression that the long-term plan is to replace it with RISC-V based solutions such as NOEL-V. Nobody can throw out working systems, but if you are starting something brand new, does it really make sense to base it on an ISA which the rest of the industry has essentially abandoned? Even its originator (or successor thereto) has basically walked away from it. Aerospace stuff is as expensive enough as it is already, getting stuck on a niche legacy ISA seems like a recipe to only make it even more expensive.

jabl7• 4 years ago

If you look at the page for the gr765 the parent poster linked to, you can see that the customer can choose the gr765 with either SPARC or RISC-V cores. I think you're right that the plan is to transition to RISC-V, given that the SPARC ecosystem otherwise is pretty moribund.

girvo• 4 years ago

I recently saw an article where a guy got Ada/SPARK up and running on one of those Gaisler chips. Was super neat to see, kind of made me want to play with Ada.

inamberclad3• 4 years ago

I love Ada, but the tooling is hell. Alire is a great start for a package manager, but it's still clunky and parallel projects like the ada language server still don't build with it for some reason.

vaxman• 4 years ago

RISC-V is NASA bad?

“Launch aborted, whenever we access the pressurization control we’re getting an ‘ISA not implemented in this version of the core’ error from the controller that arrived overnight. They must have received the wrong version of the chip and didn’t catch it in the test rig we gave them 6 years ago.” #roflmao

UltraViolence5• 4 years ago

I wonder if NASA has a clue that RISC-V's ISA is open-source but SiFive's designs certainly aren't.

Jtsummers3• 4 years ago

You can't launch an ISA into space and expect it to do anything. At some point, hardware has to be designed and built based on that ISA.

babypuncher2• 4 years ago

Nonsense; I printed out a copy of the AGC instruction set reference, stuffed it in one of my model rockets, and it turned into a Saturn V mid-flight.

UltraViolence5• 4 years ago

Then what advantage does it have over ARM or x64? The ISA being open doesn't seem to make any difference at all.

jasonwatkinspdx• 4 years ago

Yes, it's very likely the people involved in this didn't do 30 seconds worth of googling "what is RISC-V." It's so good they could wait around for our unique insights here.

I swear, this place's appetite for empty lowbrow armchair dismissal is very disappointing.

jakedata2• 4 years ago

I'd love to see an implementation in silicon carbide so we could drop it on Venus, wait for it to bounce a few times and then start exploring.

https://spectrum.ieee.org/the-radio-we-could-send-to-hell

babypuncher2• 4 years ago

I always wondered why NASA never sent any surface probes to Venus, until I read about the insane engineering (and lots of trial and error) that went into the Soviet Union's Venera program. Despite all that effort, the successful Venera probes only lasted minutes on the surface before failing.

giantrobot4• 4 years ago

The fact a lander is only going to return an hour (at best) of science data is why NASA hasn't bothered with Venus. There's a low chance of initial success and then no real opportunity for a mission extension if things actually go well. A Mars lander returns a lot more science per dollar than a Venus lander will.

jvanderbot3• 4 years ago

For context: "This contract is part of NASA’s High-Performance Space Computing project". I used to work with the HPSC leads and paid attention to it. This is one of many parallel threads for next-gen computing, including snapdragon and others. Yes, it will be rad-hard. That was a program requirement and is mentioned in the press release. As such, it fits a particular mission profile.

There is no existing compulsion for missions to use HPSC. This is a technology development program seeking to meet the requirements of missions. It's great news they converged on an architecture!

As part of their development, HPSC folks will seek mission partners for tech demos. Then, missions will voluntarily (or with some light compulsion) adopt the technology based on the growing heritage and mission need.

aidenn0• 4 years ago

Radiation hardened targets seem to stay around for a long time, judging by how many 750s are still around, so I suspect we'll see RISC-V around in aerospace for quite some time

ncmncm7• 4 years ago

This is really pretty strange.

RISC-V is a respectable enough architecture, but not better than recent POWER designs, equally open. NASA has an enormous amount of experience with POWER.

I suppose it comes down to what bidders are offering to build for them.

justahuman743• 4 years ago

Sometimes there are documents that say why NASA chose what they chose, there might be one for this

ilaksh• 4 years ago

Isn't RISC-V touted as the new open architecture going forward? Much more so these days than Power.

jabl7• 4 years ago

I'm sure NASA has an enormous amount of hard-earned in-house expertise in rad-hardened electronics, hard real-time safety critical software, and related things. But how much of that knowledge is tied specifically to the POWER ISA? Not much, would be my guess.

I've been following POWER at a distance, and while I'm sure the ISA itself is good enough, I'm not really convinced about the vitality of the ecosystem. The only place where serious money is being invested is in the high-end CPU's which IBM keeps developing enough to prevent their high-end captive customers from defecting. But at the lower end and embedded, it's crickets. Beyond some token efforts like the microwatt for FPGA's and an old supercomputer core design they open sourced, the whole OpenPOWER effort seems to be little more than a couple of guys producing the occasional powerpoint and press releases.

blihp2• 4 years ago

Not really... they're at opposite ends of their life cycles. POWER is a dying, dead-end[1] architecture while RISC-V is just getting started. Open sourcing something already in steep decline won't typically bring it back unless there are no other options.

[1] The only people who have any incentive to invest in it going forward are those who already have significant investments in it.

jvanderbot3• 4 years ago

Last I checked, another program feature is help from domestic customers that require rad-hard, high-performance chips. That may influence the architecture significantly. In theory, domestic customers add significant resources and speed to the program.

MisterTea• 4 years ago

Power? How about LEON And other rad-hard Sparc processors from Microchip (formerly Atmel)?

Looking at the problem long term RISC-V makes more sense. RV has a lot of steam building behind it and we have really neat things like the Polarfire SoC and many more in the works. New tools, compilers and software support are being added every day (hell, there is a plan 9 Risc-v compiler already...) RV is the future from the look of things.

Power has an EoL set of chips from NXP which were former Freescale/Motorola designs and costly server chips from IBM. Arm ate their lunch in the embedded sector and Intel in the desktop/server sector. No one is looking to build new Power chips. No one is porting to Power unless its a Raptor Computing Talos workstation or IBM box, essentially an expensive toy or big iron, niche stuff.

Symmetry• 4 years ago

The molecularity of the RISC-V architecture is going to be very appealing for embedded roles like this. That flexibility can be a liability for, say, a desktop operating system but if you've got an embedded system like a space probe where you develop the hardware and software in parallel it means that you can only pay for what you use in terms of ISA features. Need 64 bit memory addressing to handle all the RAM on your graphics card but don't need the chip to have an MMU? You can do that within the RISC-V spec but not within POWER. And with RISC-V there are ways to add your own specialized instructions for your particular use case.

If I were designing an open source processing for a laptop or cell phone I'd use the POWER ISA. But for a space probe I'd certainly go with RISC-V.

jvanderbot3• 4 years ago

jabl7• 4 years ago

Does that, in practice, mean military, or civilian aerospace?

pvillano• 4 years ago

I could imagine HPSC being useful for edge "compression" of sensor data. A continuously running high speed camera (or whatever they're doing at the LHC) generates terabytes of data per second, too much for direct download. The satellite has to be able to do analysis or at least process the data into a manageable stream before sending the results to earth.

mattcaldwell• 4 years ago

RISC architecture is gonna change everything.

tinktank• 4 years ago

It already did.

killingtime74• 4 years ago

ARM is already RISC. Majority of smart phones in the world

arcticbull3• 4 years ago

Basically all processors today are RISC.

Event the venerable behemoth x86(_64) has a front-end which translates CISC instructions into RISC-like micro-ops.

The distinction is pretty meaningless today.

snvzz11• 4 years ago

Micro-ops are a microarchitecture implementation detail. They are also used by many RISC microarchitectures, and are ultimately irrelevant to ISA.

Ever since the RISC paper, every new architecture of any remaining significance today has been RISC. Today, it makes more sense than ever[0].

The only CISC that remains in large-scale use is x86, which I expect to finally be deprecated during this decade.

0. https://itnext.io/risc-vs-cisc-microprocessor-philosophy-in-...

keepquestioning2• 4 years ago

Guess its time to learn RISC-V. Any good courses?

Aperocky• 4 years ago

Unless you're into compilers and whatnot, it shouldn't be necessary?

keepquestioning2• 4 years ago

You need it for OS or RTOS design

brucehoult4• 4 years ago

If you already understand assembly-language programming for some other ISA then you'll have no trouble following straight from the RISC-V reference manual:

https://github.com/riscv/riscv-isa-manual/releases/download/...

Plus recently ratified extensions:

https://wiki.riscv.org/display/HOME/Recently+Ratified+Extens...

RockingGoodNite2• 4 years ago

I wonder if NASA would be interested in my 1980 Timex Sinclair 1000?

krallja• 4 years ago

Why, is there an RFP for doorstops?

RockingGoodNite2• 4 years ago

RISC-V wasn't that bad. Lol. /s

kfihihc• 4 years ago

StarFive announces new JH7110 SoC and SBC based on SiFive U74 CPU core[1].

You can experience SiFive's product in the real world.

[1] https://www.kickstarter.com/projects/starfive/visionfive-2

preisschild• 4 years ago

Pine64 is also releasing their own JH7110-based SBC soon[1].

Antmicro also teased their low-density SoM board [2] last year, but I have not heard any news about that since, which is a shame because you could put a ton of those in a server rack.

[1] https://www.cnx-software.com/2022/08/29/pine64-star64-sbc-st...

[2] https://www.cnx-software.com/2021/04/30/antmicro-arvsom-offe...

sylware• 4 years ago

Write once assembly with a simple macro-assembler, run "everywhere"...

amelius• 4 years ago

Glad they are not sending entire M1 MacBooks into space for lack of individual M1 silicon modules.

gjadi2• 4 years ago

What is "ratification intelligence"?

From the article:

The HPSC processor and X280 compute subsystem is expected to be useful to other government agencies in a variety of applications including industrial automation, edge computing, ratification intelligence, and aerospace applications.

I couldn't find a good answer online.

cestith6• 4 years ago

I couldn't find a formal definition quickly from my sources. However, it appears in context in a few places and it seems to use the sense of "ratify" meaning "to confirm" or "to validate". "Ratify" and "ratification" are used in places where one might expect to replace it in the prose with "verify" or "verification", as in using multiple different intelligence sources (video, photo, signals, live, etc) to build confirmatory evidence of something when multiple overlapping sources exist rather than trusting a single source.

sheepybloke2• 4 years ago

A chip like that could be used for sensor fusion and validation, calculation validation, and a lot of other things. For example, if you have three IMUs doing your positioning, you could use this to ratify and validate that they are all working correctly or throw out an answer if one disagrees with the other. I've generally thought of using an FPGA for this sort of work, but a certified and inexpensive coprocessor would work well for this use case.

gjadi2• 4 years ago

Ok, so that's related to consensus algorithm.

Thank you!

NASA selects SiFive and makes RISC-V the go-to ecosystem for future missions

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