Intel delays chip-making changes

http://www.bbc.com/news/technology-33549916

by willvarfar • 11 years ago

145 173 11 years ago

MCRed3• 11 years ago

I saw another article that referred to this as a sign of the slowing of Moore's law. However, Moore's law has its variances so I'm not really worried about that.

What I do wonder about is why we are not seeing more cores as we go down to smaller nodes. 2 and 4 cores are common now, but have been seemingly for a decade. Why aren't we seeing 8, 16, 32 and 64 cores? If you reduce the feature size and effectively thus double the surface area available, why not increase the cores? It seems the new area is going into integrated GPUs (never as good as discrete GPUs, but certainly cheaper) and cache. Cache can improve performance but not like more cores. While intel does a tick/tock design revision, each core seems to grow to fit the available space, with only adding a few instructions, which only add marginal utility. Not the same as doubling the number of cores, which would double theoretical performance.

Under Erlang/Elixir, we are able to get close to linear speedup from additional cores. I understand other languages struggle with multi-threaded programming, but should CPU designs be hobbled simply because the software industry is not where it should be?

Am I missing something?

sfilipov• 11 years ago

I think you found the answer already. Already there are server processors with a lot of cores (i.e. 20) - if you can utilise them all then buy one.

However, for most client workloads, more cores does not translate to better performance because many of those cores will just idle. Single-threaded performance is still the king.

hmottestad• 11 years ago

18 cores seems to be the best that Intel does. Which is fairly decent. http://ark.intel.com/products/84683/Intel-Xeon-Processor-E7-...

In laptops, there has been a trend for thinner, lighter and long battery life. So the easiest is to lower power demand. If you increase the number of transistors (by adding more cores), power consumption wouldn't go down enough.

robin_reala2• 11 years ago

Xeon Phi currently has 61 cores[1] (62 on-die, 1 deactivated for yield reasons), and the next generation coming soon pushes that to 72 cores.

[1] http://www.intel.com/content/www/us/en/processors/xeon/xeon-...

yareally• 11 years ago

We do have 8, 12 and 18 core CPUs made by Intel. They're just expensive and not made for the typical consumer. My PC at work has the 12 core Xeon. It's nice for compiling large projects, but at home I'm content with a 4 core i7.

http://ark.intel.com/m/products/75283/Intel-Xeon-Processor-E...

http://ark.intel.com/m/products/81061/Intel-Xeon-Processor-E...

HappyTypist• 11 years ago

Smaller die areas have complications of its own -- heat has less space to travel. It's not as simple as "half the die area, double the cores" -- if you do that, you will end up overheating.

But I think the main issue, as you mentioned, is multi-thread programming. Everyday users spend most of their time in a browser, running Javascript which is mostly synchronous. There are web workers, etc, but the vast majority of sites are still running single threaded JS.

jsprogrammer6• 11 years ago

People may want to run multiple simultaneous threads though, which is what additional cores excel at.

jsprogrammer6• 11 years ago

We do see 8 and 16 cores.

Newegg currently lists 10 different 8-core desktop processors and 120 different 8-core server processors. There are also 10-, 12-, 14-, and 16-core processors available to purchase right now.

habitue• 11 years ago

Two things I can think of: for consumers, applications don't currently make the best use of multiple cores. There just isn't enough work to do on them. For gaming at least, DirectX 12 will remove a limitation that only one CPU core can control the GPU at a time. That may push demand for more cores upwards over time.

Second is that cache coherence gets really ugly the more cores you have with a single shared memory. From what I understand, this is a limitation of assumptions in the x86 architecture. A completely new architecture might sidestep the problem, and indeed I've heard of 1024 core machines etc, which I doubt have just brute-forced cache coherence.

socceroos2• 11 years ago

DX12 - catching up to Mantle and Vulcan but ahead in marketing.

marcosdumay• 11 years ago

You are missing that yes, CPU designs are hobbled by the software industry shortcomings.

Also, you are overlooking that on the traditional architectures memory access becomes slower the more cores you add.

Better integrated GPU and better power consumption on PCs will win on almost all scores until the integrated GPU becomes good enough, and power consumption gets near the theoretical minimum. Then we'll probably see alternative architectures (more alternative than a GPU).

pjc503• 11 years ago

Clearly we should boot the operating system straight onto the GPU.

(Joking, but also a great project if you have an army of graduate students to keep busy)

detaro• 11 years ago

for desktop systems, small number of fast cores is still better than multiple slower ones, since a lot of the software that would profit most isn't very well optimized for making use of many cores. IMHO there is not that much demand for better performance in bread-and-butter CPUs anyways, things like embedded graphics, power saving etc matter more.

The top desktop CPUs have 6 or 8 cores, and Intel Xeons go up to 18.

And there are the Intel Xeon-D and Atom Cxxxx, which go in the direction of having (at the moment up to 8) smaller cores and low energy usage, for tightly packed servers and networking devices. I guess once they get more established they might get higher-power counterparts with more cores.

And the Xeon Phi might get there, if Intel manages to do what they promise for future generations.

each core seems to grow to fit the available space, with only adding a few instructions, which only add marginal utility. Not the same as doubling the number of cores, which would double theoretical performance.

The progress between generations isn't big enough to allow doubling the core count in the same envelope with the same per-core performance. So they only make the cores a bit better & slowly add a few cores (mostly to the high end).

high-end phones actually have quite a few cores in the meantime, but there they are staggered for different usage scenarios: a few slow, efficient cores combined with faster and more energy-hungry ones for high-performance tasks. But for most x86 systems that would "waste" to much of the chip I guess.

but should CPU designs be hobbled simply because the software industry is not where it should be?

Designing CPUs for "the perfect software" is nice, but not what sells to the vast majority of the market. As listed above, there are quite a few niche lines that go in that direction, even if you just look at only Intels offerings.

TheOtherHobbes• 11 years ago

There's no demand for better performance given current architectures and applications.

It's not hard to imagine more interesting architectures and applications - for example associative language processing, supercomputer-powered robotics, games and UIs that have true cinematic 3D photorealism, or gestural 3D interfaces with very large retina displays.

The problem is really the pace of OS and UI design. We're still using the Xerox Parc GUI model forty years after it was invented, the POSIX OS model some fifty years after it was invented, and the sequential Von Neumann architecture sixty years after it was invented.

These were all breakthroughs at the time, but they should never have become the last word. Research of equivalent creativity seems to have stalled now. IMO it's not just because the low-hanging fruit has been picked, but because there are commercial, academic, and political pressures holding it back.

There may be a game changer generation ten or twenty years from now. But it looks like the pace will be slow until then.

dragonwriter3• 11 years ago

Why aren't we seeing 8, 16, 32 and 64 cores?

Intel has 8-core i7s, up to 18-core Xeon processors, and up to 61 cores in Xeon Phi coprocessor packages.

If you reduce the feature size and effectively thus double the surface area available, why not increase the cores?

Because, outside of narrow domains, software that can effectively use lots of cores doesn't exist, so you don't provide good bang for the customers buck by doing that. For most customers, there's no utility for that.

Cache can improve performance but not like more cores.

And vice versa -- more cores can improve performance, but not like cache. Which is more useful depends on software and workloads.

Under Erlang/Elixir, we are able to get close to linear speedup from additional cores.

On the right kind of workloads. And, the people with those kind of workloads, have many-core processors available.

cft• 11 years ago

Any web server that serves at scale can readily use 1024 cores... Nginx, servers built in Go, Erlang and many more. It would reduce hosting costs and complexity substantially.

jotm2• 11 years ago

More cores is always a good choice for consumer chips - even if one program doesn't effectively use them, running multiple applications in parallel sure as hell does.

And these days, we're running everything under the virtual sun and expect it to work fast and smooth :-)

adwn2• 11 years ago

Under Erlang/Elixir, we are able to get close to linear speedup from additional cores.

The two main obstacles with parallelization are

1) dividing a problem into a large number of sufficiently parallel tasks, and

2) communication costs.

Erlang isn't a magical bullet that solves these problems. An inherently sequential algorithm doesn't become parallel only because you can cheaply spawn thousands of green threads, and inter-core communication doesn't become faster just by having a convenient message passing mechanism.

Regarding the downvotes: My guess is that you're not being downvoted because of your dissenting opinion, but because you're presenting a misinformed opinion as fact.

narrator• 11 years ago

If Moores law ends with 14nm, I wonder what we'll be doing 10 years from now.

fdej• 11 years ago

I guess we'll be removing cruft from the web.

astrodust2• 11 years ago

Porting to HTML6.

minthd3• 11 years ago

Maybe(in 10-20 years) We'll build analog imitations of the brain , with similar density and high power efficiency.

Or maybe we'll build other types of compute machines using analog electronics.

Maybe we'll replace digital multiplies with pseudo digital multipliers that use analog computation the background, and with other forms of non-exact computation.

Or We'll use photonics to analogically compute FFT's to multiply matrixes.

Or maybe we'll finally seriously and successfully invest in optical digital computing.

Or we'll crack quantum computing.

pjc503• 11 years ago

Analog and "non-exact" computation is not something that sounds very useful. The only reason we've been able to minimise so much is the tremendous noise rejection of binary systems.

Besides, modern computers are spending most of their time on actions of marginal or negative utility, mostly data-bureaucratic rather than computational.

roghummal5• 11 years ago

Maybe(in 10-20 years)

I've seen 20 years of progress. Yeah... not to discourage you; Keep on shooting for the stars.

Quequau• 11 years ago

There was an excellent presentation at HotChips 2013, given by Robert Colwell from DARPA on that topic.

solomatov• 11 years ago

It's available on youtube https://www.youtube.com/watch?v=JpgV6rCn5-g

ghaff• 11 years ago

That's an interesting presentation in that it outlines a lot of the directions--including rather novel ones--that processor technology could potentially be taken. He also emphasized more system-level thinking.

At the same time, he also emphasizes just what an amazing technology CMOS has been and how that's made it such an important part of the computer revolution of the last 30 years. So, no, it's not like progress will stop but without the tailwind that CMOS scaling supplied, I expect the rate of advance in a lot of areas will slow down. (As, indeed, we're seeing on desktops and laptops today even if there are also other dynamics in play.)

Keyframe• 11 years ago

Add more chips / cores!

logicallee• 11 years ago

look back and laugh at how long we were able to just shrink transistors within the 1 plane, totally ignoring all depth? Remember, moore's law is about transistor count per square inch. I'm kind of shocked we don't use 3D chips, though I understand heat is an issue.

Retric• 11 years ago

Chips are 3d, Intel for example uses 13 layers. There are massive heat and cost issues when adding layers, but flatter chips have latency issues. Stacking chips is also common in cellphones and other low power designs.

pjc503• 11 years ago

Manufacturing process is the main issue. Too many layers and it's impossible to keep flat enough to build the next layer on. Chip-on-chip is however becoming widespread, keeping your DRAM nice and close.

kllrnohj2• 11 years ago

AMD's new desktop GPUs use 4 tall stacked memory modules. Stacked chips are definitely a thing. When this makes its way to compute modules remains to be seen, though.

noir_lord• 11 years ago

Using languages with low(er) complexity parallelism, optimising existing code as much as possible and (possibly) writing code for FPGA's (modern processors are pretty good at doing lots of things reasonably well but workload tuned FPGA's kill them and 10 years of FPGA research after a boatload of cash could be interesting).

Also if we are bottoming out on Silicon then investment into other technologies should pick up, Graphene and the like.

It should be exciting, Intel has had a lock on the desktop processor market for over 30 years (by volume if not technical excellence at some points).

craigjb• 11 years ago

There is also a lot of space between general purpose CPU and completely blank-slate FPGAs. GPUs are essential very wide data word processors (one instruction but a large data vector).

And, there are also configurable pipeline processors that consist of multiple ALUs (can be vector data) with reconfigurable connections between them. So rather than eat the overhead of generic bit LUTs in an FPGA, you reconfigure the interconnect in a fabric of ALUs. The fabric can contain specialized ALUs (or execution units), and varying densities depending on typical usage. This avoids a the technology mapping and place & route of FPGA design. Translating a description of hardware (HDL) into actual lookup table data is a massive compute problem for large modern FPGAs. However, if we collapse the routing to just data buses between compute units, the problem can be solved in real-time. This way, a compute pipeline could be reorganized by an application at run-time without using a full-fledged hardware description language with all kinds of very low-level constructs. Higher-level language compilers already exist for this kind of architecture in academia.

EDIT: The sea of ALUs can also contain memories, FIFOs, and other block elements. However, they would all operate on the same word size to reduce the routing problem and allow maximum density implementation.

In fact, this is the essence of how micro-coded instructions in a modern CPU work anyway--instruction 'scheduling' is basically figuring out how to route data transfers in a sea of execution units.

The article "Fundamental Underpinnings of Reconfigurable Computing Architectures" in the March 2015 Proceedings of the IEEE contains a wonderful introduction to all these concepts.

mrb• 11 years ago

It is very obvious what we will be doing, and this has been discussed many times: add more metal layers.

Intel processors only have a dozen layers which stack up to less than ~1 um. The numbers of transistors/layers could in theory be increased by 1000x if the layers were stacked ~1 mm high. How to do this with lithographic processes is an open question, but it is absolutely doable in theory. No physical limits prevent us from doing that.

knd775• 11 years ago

Heat would be a massive issue with more layers, right?

nhaehnle• 11 years ago

How to do this with lithographic processes is an open question

You don't, for economic reasons: the latency of chip manufacturing, i.e. time from initial wafer to finished, is already on the order of weeks. Producing more layers lithographically is going to multiply that latency. Not to mention that it would be a nightmare in terms of yield/manufacturing defects.

What is doable (and already done, I believe) is producing multiple chips in parallel and then stacking them on top of each other. Don't think cores spread across multiple layers; think alternating layers of cores and caches, or a layer of cores with layers of memory stacked on top. (This approach doesn't have the yield problem because you can test the chips before you stack them together. It's a technology that is going to see a lot of improvement still.)

Heat transfer is still a problem, though, simply because the number of transistors scales with the volume, i.e. cubically in the "radius", while the surface area available for heat transfer only scales quadratically.

P.S.: When chip people talk about "metal layers", they mean the layers of wiring (also called the BEOL, back-end-of-line). So increasing the number of metal layers does not actually increase the number of transistors. Also, when chip companies talk about "using N layers" in their current technology, that does not mean that N transistors are stacked on top of each other. It means that there is one layer of transistors, and N layers for connecting wires above.

sliverstorm• 11 years ago

What? How does adding metal layers allow you to increase the number of transistors? Transistor density is a fixed function of transistor size, and die size is a variable function ruled mostly by defect density. Unless you are talking about die stacking?

tedsanders2• 11 years ago

This is not obvious at all. Going 3D makes sense for memory, because these devices aren't heat-limited, but for CPUs it's not at all clear that stacking layers would be a win. CPUs are limited by heat, and heat transport away from the CPU is proportional to area, not volume.

Also, CPU costs are driven mostly by lithography, and if you're doubling the number of high resolution lithography steps, you aren't saving much money compared to just making larger area CPUs.

AnimalMuppet2• 11 years ago

There's also the little matter of defect density. Let's say your 10-layer process yields 50%. Now you go to a 20-layer process, and you should expect your yield to drop to 25%.

(I know, it's not that simple, because there are some defects that are in the underlying substrate. I'm ignoring those for purposes of this discussion.)

JohnBooty4• 11 years ago

As others have noted, workload-specific FPGAs are very promising.

Another big bottleneck is memory latency. For each cache miss, a modern CPU spends hundreds or even thousands of clock cycles doing nothing. A majority of the transistors in your CPU are dedicated to mitigating this in one way or another - the L1/L2/L3 caches, transistors dedicated to branch prediction, etc.

I don't know what the outlook for improving the memory latency situation is. It's probably going to involve gobs of on-chip embedded RAM, which is expensive.

roghummal5• 11 years ago

What good is an FPGA if it isn't 'workload-specific'? That's what they do. That workload might be a processor, it might be an interface, ... you get it.

Workload-specific FPGAs are here, now. They're not 'promising' because they're doing exactly what they were made to do!

I don't know what the outlook for improving the memory latency situation is. It's probably going to involve gobs of on-chip embedded RAM, which is expensive.

They already have a name for that and you already named it.

It's called cache ;)

SEJeff• 11 years ago

Writing CRUD apps, the same thing that we've always been doing overall as an industry :)

the8472• 11 years ago

Moore's law ending just means progress will slow, not cease.

But in addition to that there are other things we could optimize. For example a lot of transistor budget is spent on caches and very clever out of order execution. If memory bandwidth could be increased to the point where those deep out of order pipelines aren't needed anymore to mask memory latency then maybe we could utilize the chip area better.

SRAM used for caches also eats a tremendous amount of space and power due to its 6T, always-powered design.

Imagine MRAM (1T, non-volatile), manufactured in the same process node as the CPU itself, stacked right onto the CPU and/or connected with light-based transports. Since MRAM doesn't need to be powered when it's idle it would also allow for rapid power-switching, thus giving the chip designers more thermal headroom.

Another thing: Remember how chips used to shrink and increase in clock speed? Well, the gigahertz race has been over for a while. But if they use the longer process-nodes to introduce new technologies (different semiconductors, carbon nanotube conductors, ...) then there might be new room to push a few extra GHz.

Progress will certainly slow and at some point it'll require radical re-designs, but there's still a lot of room for improvements.

jjoonathan• 11 years ago

SRAM used for caches also eats a tremendous amount of space and power due to its 6T, always-powered design.

What gets in the way of using SRAM for main memory? I've always been told that it's the space multiplier (6T vs 1T+1C) but that never seemed terribly convincing because DRAM is cheap enough (and has been cheap enough for a while) that it would make sense to pay a 3x-5x premium to avoid page open/close latency even in the high-end consumer market. Heck, many consumer devices are already 2-4x overprovisioned with DRAM just in case someone doesn't like closing chrome tabs (or whatever).

By process of elimination I tend to suspect it's the power draw, but it seems odd that power from leakage current on inactive SRAM gates would dramatically exceed that of DRAM's active refreshes.

What gives?

roghummal5• 11 years ago

Intel's 7nm? Anyone?

jolan2• 11 years ago

I hope Intel uses this pause to implement things like DJB's suggestions for the Intel instruction set:

http://blog.cr.yp.to/20140517-insns.html

notatoad• 11 years ago

When a company delays a product launch, it's usually because they have too much work to do, not not enough.

RandomBK• 11 years ago

No, it means that some departments have too much work. Other teams and task forces can use this time to experiment with new stuff.

awalton• 11 years ago

Intel didn't delay a product launch, they delayed a PROCESS launch, which is a much bigger deal given their previous cadence towards the bottom. Physics is kicking the silicon industry's ass.

Meanwhile, the guys doing HDL and verification at Intel don't even notice the process delay, they just go about what they're doing, leaving them plenty of time to implement whatever (namely GPU improvements, which is what most of the industry has been requiring for newer Windows/Mac OS Xes).

pbsd• 11 years ago

They already have. The upcoming AVX-512 extensions [1] introduce the VPMADD52LUQ and VPMADD52HUQ instructions, which add the high or low 52 bits of a 52x52-bit multiplication to a 64-bit integer. Presumably this is done via the preexisting double precision floating-point multipliers.

[1] https://software.intel.com/sites/default/files/managed/0d/53...

jolan2• 11 years ago

IIRC, upcoming to Xeon Skylake processors not mainstream ones.

higherpurpose• 11 years ago

When first formulated by Intel co-founder Gordon Moore 50 years ago, this suggested that chip power could double every 12 months.

What? I don't think it was ever 12 months, but 18-24 months.

Now, improvements are expected approximately every 24 months.

No, they said it will take 2.5 years now instead of two.

http://seekingalpha.com/article/3329035-intels-intc-ceo-bria...

I wouldn't expect the 10nm chips at least until mid-2017, which should put Intel neck in neck with TSMC and Samsung's 10nm processes, which at most might be launched a few months later.

It also looks like IBM and its partners (Samsung/Global Foundries) will actually beat Intel to 7nm (probably early/mid 2019 for Samsung/GF - late 2019/early 2020 for Intel).

While IBM is talking about EUV lithography, Intel still seems to be complaining about multi-pattern lithography, so it seems pretty clear that Intel is behind IBM for 7nm. They also haven't said anything yet about what materials they'll use for 7nm transistors, just that they will require something different than Silicon.

The best part about this is that now Intel can't hide the x86 baggage in mobile behind its one generation ahead process node, which made Atom more or less competitive (at least in performance and power consumption, but not in price).

With ARM chips on very similar process nodes and arriving at the same time on the market, there should be no contest for the ARM chips in mobile.

robin_reala2• 11 years ago

Also it’s not ‘chip power’ but ‘number of transistors’. Common misunderstanding.

jfoutz• 11 years ago

Yeah, even without the step to 10nm, the third generation 14nm chips will probably be a bit faster than the second generation. Density can't be improved but there is surely efficiency to be realized.

qdog2• 11 years ago

Not clear what IBM doing 7nm means, really. They no longer own a foundry, and don't have any chips in normal products that compete with Intel. IBM also demonstrated some really high clock speeds previously, but the Power8 is still a 4GHz part and is built on 22nm.

Now, if Global Foundry actually starts making full 14nm chips this year (which it doesn't sound like it, seems to be a 20nm back end), that might things pretty interesting.

I previously worked for a company that used both TSMC and UMC, the jump to the next process level is always extremely hard, and the biggest deal is yield. Until the yields are high enough to actually get to a profit a lot of companies with specialized chips will stick to the older process (set-top box chips for instance) where it's good enough.

FD: I'm at Intel (not hardware), cannot comment on Intel itself.

bitmapbrother2• 11 years ago

Why does IBM need to own a foundry to design chips? Making chips is a commodity business. The skill is in the design and patenting.

NateLawson• 11 years ago

Gordon Moore first proposed 12 months in his article, then dropped back to 24 months a few years later. That number has held since the 80's, until now.

saosebastiao• 11 years ago

But will it have non-disabled HTM?

EDIT: Its a real question. Working HTM would negate pretty much any bad news from Intel in my mind.

aburan282• 11 years ago

I just read about how they were delaying the AVX512 until 'Knights Landing' (Xeon Phi) and with Haswells mediocre improvements Intel has really not come up with anything substantial in years. Hopefully the recent Altera acquisition will help them innovate

chinhodado• 11 years ago

with Haswells mediocre improvements Intel has really not come up with anything substantial in years

Not really. This statement is true regarding desktop CPUs, but we all know for at least five years now Intel's focus is not desktop CPU performance anymore, but mobile. Hence most of the improvements we see are for mobile, like better embedded graphic (Sandy/Ivy Bridge forward) and improved power consumption (Haswell).

wtallis2• 11 years ago

Intel really shouldn't get credit for the Sandy Bridge IGP, because that's just where they caught up to the NVidia IGPs that they'd banned. The first generation of Core series mobile chips represented a major step backwards from the user's perspective because Intel would no longer let NVidia make chipsets, so Intel's IGPs no longer had to compete against the GeForce 9400M and 320M. Ivy Bridge was the first time Intel actually moved the market forwards in terms of mobile IGP performance.

vardump5• 11 years ago

with Haswells mediocre improvements Intel has really not come up with anything substantial in years

Unlocking Haswell's performance (up to 2x integer/FPU) requires using AVX2 instructions. Which means at least recompiling and to truly extract the performance, optimizing to AVX2 intrinsics or assembler.

oldmanjay• 11 years ago

Did the BBC forget a comma in the title? I'm having a hard time parsing it.

Edit: or perhaps a dash? Really it's just a horrible title all around.

mikeash2• 11 years ago

I don't think so. They are delaying changes to their chip making process.

Cyph0n• 11 years ago

Yes, a dash; “chip-making changes” makes much more sense. Horrible title indeed.

aburan282• 11 years ago

Moore's law plateaued years ago. Sure they are adding more cores but thats because they have made no progress on the clock speed in nearly a decade. FPGA's are going to be the next go to for performance until cpu clock speeds improve

mikeash2• 11 years ago

Moore's Law is about transistor count, not clock speed. They used to go together, now they don't, but Moore's Law is still doing OK. This is an indication that it may be coming to an end, finally.

bargl• 11 years ago

Richard from DotNetRocks does an Awesome show on this. https://www.dotnetrocks.com/default.aspx?showNum=1130

singlow• 11 years ago

I thought Moore's law had more to do with density than clock speed. I thought that increased density helped to increase clock speed but that was not really Moore's Law. Recent increases in density have not helped clock speed as much due to other constraints on clock speed, but the density has still been increasing, hasn't it?

astrodust2• 11 years ago

Smaller transistors can flip state more quickly with less energy, so usually a die-shrink allows higher frequencies.

There's a limit to how much you can crank these things before power consumption becomes ridiculous and heat dissipation is impossible.

You can make a 10GHz CPU if you're prepared to require a massive liquid helium cooling system and have a power consumption of 15KW.

JohnBooty4• 11 years ago

    Sure they are adding more cores but thats because 
    they have made no progress on the clock speed in 
    nearly a decade.

Per-core IPC (instructions executed per clock cycle) have soared since then. That's why a modern 4-core Core i7 is roughly 20-30x faster than a "Netburst" Pentium 4 from 10 years ago.

Looked at another way, each individual core of a modern i7 is about 5x-7x faster than those old Pentium 4 CPUs.

http://ark.intel.com/products/27495/Intel-Pentium-4-Processo...

    FPGA's are going to be the next go to for performance until 
    cpu clock speeds improve

Maybe. What would also be cool is decreasing the latency of main memory. That is the current single biggest bottleneck in processors today. A cache miss usually means that the CPU sits around doing nothing for hundreds of cycles while it's waiting for data to be fetched from main memory.

dragonwriter3• 11 years ago

When first formulated by Intel co-founder Gordon Moore 50 years ago, this suggested that chip power could double every 12 months.

Actually, when first formulated by Moore, it was that transistor density doubled every 12 months (he later revised it to 2 years.)

Per Wikipedia, it was David House who applied it to performance (and, when he did, it was with an 18 month timeframe.)

tedsanders2• 11 years ago

Actually, when first formulated by Moore, it was that transistor density doubled every 12 months

No, it was the number of integrated components on a chips, not transistor density.

Anyway, I think the article's statement is fine. Doubling the number of components would suggest that performance doubles too.

brianwawok• 11 years ago

Does a car with 12 cylinders drive twice as fast as one with 6? Or accelerate?

Performance is too complicated to just say "CPU X doubles perf".. because likely some perf cases stayed the same, some got better, but some got worse (think deep pipelines).

walterbell3• 11 years ago

Bunnie Huang on Moore's Law, http://www.wired.co.uk/magazine/archive/2015/08/features/moo...

“.. WIRED buys the iPhone 6 schematic book (above) for 25 RMB (£2.70) .. It's like getting a master class on circuit design .. for £2.70, engineers in China can get a leg up on the best and brightest university-educated kids by studying these designs ..

.. there are established, legitimate businesses that earn their keep creating schematics from circuit boards. As the pace of Moore's law diminishes, learning through reverse engineering will become increasingly effective, as me-too products will have a larger market window to amortise reverse-engineering efforts before the next new thing comes along.

.. Even a modest deceleration of Moore's law can have a dramatic effect: a five per cent reduction in the pace of gate-length shrinkage -- from 16 percent to 11 per cent per year -- increases the available time to develop products within a technology generation by 50 per cent, from two years up to three.

.. Instead of running in fear of obsolescence, open-source hardware developers now have time to build communities around platforms; we can learn from each other, share blueprints and iterate prototypes before committing to a final design.”

benjaminl• 11 years ago

Great observation except a reduction of 16% to 11% a year is closer to a 30% reduction in pace. Although this only makes the point stronger. If we are indeed on a 3 year cadence instead of 2. This is a significant change in the rate of More's law.

ghoul2• 11 years ago

Does that also not imply that the this "freedom" to clone would start coming under increasing pressure from IP owners?

Till now, chip companies were too busy upgrading and innovating their products - as long as that was profitable (cause clones were always a few steps behind), they weren't too intent on IP action. But with the clones catching up, maybe we will see increasing RIAA-style actions? No more easy imports of clones from aliexpress, etc?

wtallis2• 11 years ago

We already went through that scare and got the Semiconductor Chip Protection Act of 1984 to supplement what was already protected by patents.

analognoise• 11 years ago

If you owned a printer and you reduce the size of your printing by half (in each direction) you quadruple your efficiency - it is an area equation, not a linear ine. I'm surprised that slipped past Wired...

KeytarHero• 11 years ago

Well, they did mention that elsewhere:

Shrinking gate lengths have meant 30 per cent more transistors per year for the same-sized fleck of silicon (transistors are laid out in a two-dimensional array, so gate-length scaling improves density in two dimensions).

I'm guessing they deliberately went with a not 100% accurate statement just to get their point across more elegantly - especially since the statement is still correct if you take "font size" to mean "font area" (even though that's not the typical understanding of font size).

tzs• 11 years ago

Where did the designers who designed the iPhone 6 learn?

walterbell3• 11 years ago

Monty Python, "Four Yorkshiremen", https://youtube.com/watch?v=Xe1a1wHxTyo

rer0tsaz• 11 years ago

House for the Feeble Minded.

adventured• 11 years ago

Which is another way of saying, even more value will shift to the software side and away from hardware.

harshreality• 11 years ago

Chris Mack has been vocal on this. And not only was he probably right about Moore's Law (defined as scaling that decreases the cost per transistor) being dead last year[1] (the cost per transistor curve has been flattening out), but now Intel can't even keep pace with process shrinks at any price the market will bear.

That doesn't mean progress will stop, however[2], but rather that progress (and a revised definition of Moore's Law) will be defined by chip redesigns and particularly specialized functionality that doesn't take many gates to implement but makes chips more valuable.

[1] https://www.youtube.com/watch?v=IBrEx-FINEI#t=1m13s

[2] http://spectrum.ieee.org/semiconductors/processors/the-multi...

Animats2• 11 years ago

Putting huge numbers of ordinary CPUs on a chip only helps until the memory bus runs out of bandwidth. For GPU-type devices, the computation/memory request ratio is higher, so GPUs can have many more compute units. GPUs are now used for lots of other parallel computations, and there's room for expansion in pure-computation GPU-like devices that don't drive a display.

Historically, unusual massively parallel architectures have been commercial failures. "Build it and they will come" doesn't work there. There's a long history of weird supercomputer designs, starting with the ILLIAC IV and continuing through the Ncube. The only mass-market product in that space was the PS3's Cell, which was too hard to program and didn't have enough memory per CPU. (The Cell had only 256KB (not MB) per Cell CPU.)

The next big thing may be parts optimized for machine learning. That's massively parallel. We may, at last, see "AI chips".

nickpsecurity12• 11 years ago

I mainly agree with that sentiment. What do you think about the TOMI tech, though?

http://www.venraytechnology.com/Making%20a%20Frosted%20Cake%...

I think it was a brilliant reframing of the problem: move CPU's to memory with its cost-benefit analysis rather than vice versa (status quo). The design also achieves what some exascale proposals are trying to achieve with R&D in terms of better integrating CPU & memory with lower energy. It's also massively parallel (128 cores) and optimized for big data. Close to your next big thing.

It's main risk right now is that DRAM vendors are more conservative and mass market than most fabs. There's not all this MOSIS, multi-project runs, and so on. Their low-volume cost is currently high (tens of thousands). They might be facing a chicken-and-egg problem in terms of hitting enough volume to get a nice, production deal. I do like their tech and think it has far more potential than what they're doing right now.

ak2172• 11 years ago

Except you still need a fast bus for the CPUs to talk to each other and to access shared memory. So for all but the most embarrassingly parallel workloads, you just move the bottleneck from the memory bus to the shared cache bus, do you not?

minthd3• 11 years ago

> It's main risk right now is that DRAM vendors are more conservative and mass market than most fabs.

recently micron released a memory based processor/state-machine architecture called "automata". This might be a good sign that the problem you mention will be solved.

da_chicken• 11 years ago

Die size isn't really about packing more cores into a CPU. it's about packing more CPUs on a wafer. The material cost is the largely the same. Smaller die sizes are about your quality control with masks and deposits.

Given a 300mm diameter wafer and a 10mm square CPU die at 14nm you get about 700 CPUs per wafer (Pi * diameter * diameter) / (4 * die * die) (https://en.wikipedia.org/wiki/Wafer_(electronics)#Analytical...). If you change that 10mm CPU to 10nm, you'll have about a 7.2mm square CPU die. That's nearly 1400 CPUs per wafer. Even if you get 100% of CPUs from the 14nm die, once your yield hits 50% on 10nm the 10nm process produces more for the same cost. Now you can either reap the profits, or reduce costs.

nightcracker• 11 years ago

I'm no expert, but isn't there another technique in play as well?

As you get smaller you can duplicate CPU components to make your chip fabrication more robust against errors. If a component is faulty on the die, the CPU can be patched to use the other (identical) component.

ak2172• 11 years ago

What defines "unusual"? The CPU/GPU split is a distinction without a difference there. NVIDIA and ATI have both been selling massively parallel architectures in their GPUs for most of a decade now, and NVIDIA has great traction in the supercomputing and machine learning space due to its HPC business development, excellent tooling and developer support. Intel is trying to do the same with Xeon Phi, and they're certainly throwing their weight behind it.

Both Intel and NVIDIA are addressing the memory bus bottleneck with chip packages that stack memory chips and shorten/widen the bus. The two are converging to similar designs and I foresee a big fight as they go head to head (remarkable, given NVIDIA's size, but not unprecedented, given how badly the ARM crowd has smoked Intel in mobile).

vardump5• 11 years ago

Intel CPUs resemble GPUs more and more over time. I think just scatter, GPU style ultra slow (high latency) but wide memory interface and texture lookup is missing in Skylake (Xeon).

Gather was already added in Haswell, although it performs badly so far.

Skylake (Xeon AVX-512) handles 16 float wide vectors (512 bits) and can dual issue per clock, bringing effective rate to 32. That's definitely comparable to modern GPUs.

Wasn't Nvidia WARP just 16 float wide per clock cycle? Or 32? For comparison, high end Nvidia 980 GTX GPU has only 16 of such SIMD execution cores. However, they count those 16 cores as 2048 in their marketing literature.

I do wonder if Intel is planning to unify CPU and GPU in 10 years or less. Things sure seem to be moving that way.

If Intel can add significant amounts of eDRAM in package, x86 CPUs aren't that far from being capable of handling GPU duties as well.

valarauca12• 11 years ago

Vector Instructions != Scalar Instructions

"WARP Scheduler" gives you a hint.

Okay, so how this works is you have a processor that is 16 scalar cores wide. Each scalar core is really just an out of order scheduler, for 32 in-order pipelined, boring, ALU's. These ALU's can each execute the same instruction, together, giving you the illusion that the scalar core is doing vector processing.

The reality is far weirder. I.E.: If you encounter a branch, the scalar processor can, and will execute both branches on different ALU's, and execute the branch statement on another, allowing for a 10 instruction section of code to run in ~3 instructions time. Trying doing that with a vector processor.

Technically in CUDA you can schedule each ALU itself, thus marketing stuff.

Would you like to know more? http://haifux.org/lectures/267/Introduction-to-GPUs.pdf

m_mueller2• 11 years ago

GPUs have evolved with about the same pacing. Nvidia's Kepler architecture has a vector length of 192 (single prec.) per core and up to 15 of these cores on one chip.

The question really is, do you optimize the chip for heavily data parallel problems, saving overhead on schedulers and having a very wide memory bus, or do you optimize for single threaded performance of independent threads and give it some data parallelism (Xeon). As a programmer, when you're actually dealing with data parallel programs, doing so efficiently on a GPU is actually quite a bit easier since you have one less level of parallelism to deal with.

pmalynin• 11 years ago

With CUDA you get 32 banks, all of which can be accessed in parallel.

throwaway2048• 11 years ago

the issue is not so much memory BANDWIDTH as it is an issue of memory latency on heavily branching code.

nickpsecurity12• 11 years ago

It doesn't really bother me as we've seen it coming for years. Anyone playing smart is not relying on a process node jump rather than better architected systems. I think the fact that they bought Altera and might do on-board FPGA logic more than balances out here. I'll take an FPGA-accelerator on their on-chip NOC over an incremental increase in performance/energy any day. Even big companies such as Microsoft are wisening up to the fact that a proper split between CPU and FPGA logic has significant advantages.

I'm curious to see what AMD will do in response to both the delays and Altera acquisition. Wait, a quick Google shows AMD to be so bad off that a FPGA company (Xilinx) might buy them. Lol. Ok, well the market is about to get interesting again one way or the other.

ep103• 11 years ago

Isn't IBM announcing they've discovered how to build 7nm chips? Things are still progressing

nickpsecurity12• 11 years ago

They'll certainly progress. Far as IBM's announcement, they said they could do it in a lab but not mass manufacturing. Intel says they can't mass manufacture things yet. So, the two could be in a similar situation where they have lab-proven concepts but nothing further. Too little data for me to know at this point.

AnimalMuppet2• 11 years ago

I don't even want to think about the antivirus implications of running FPGA code.

nickpsecurity12• 11 years ago

It could get interesting. Of course, for secure CPU developers, FPGA's have been the solution for stopping malware rather than the problem. Too bad we only have prototypes to work with so far. Remember, though, that there's always anti-fuse (write-once) FPGA's available for a design you don't plan to change.

nickpsecurity12• 11 years ago

Oh I forgot to give you this to help you sleep better at night:

http://www.cis.upenn.edu/~jms/papers/fpgavirus.pdf

monocasa4• 11 years ago

Eh, as long as it's on the other side of a hardware based IO-MMU, I'm not super concerned.

bravo223• 11 years ago

FPGA eats a ton of power. You won't see it anything consumer. It is already used in Server/Pro applications.

nickpsecurity12• 11 years ago

There's plenty of low watt FPGA's, even mW's. The Cyclones, etc get 4,000+MIPS in under 2 watts. Microsemi already does FPGA's that run milliwatts with enough slices to support 5-6 accelerators concurrently. As the example below shows, you can have two Stratix's, a CPU, and a whole board's worth of stuff using only 45watts. Merely adding a few layers to an SOC at Intel's new nodes should use way less power than all that. I'm sure Altera's, with Intel's help, will be pretty sweet given they're mainly targeting datacenter use where performance-per-watt is key criteria.

Still, worst case, I'll gladly add 45watts to a gaming/workstation rig... which probably already has a several hundred watt power supply... in exchange for Stratix IV's 500,000+ LE's, 20Mbit SRAM, 20+ 8.4Gbps transceivers, and more direct CPU-to-FPGA link. You have no idea what I can do with that amount of logic and interface speed. A whole OpenSPARC T1 setup only takes 173,000 LE's. Most extensions to make highly secure processors take up a small fraction of that.

So many possibilities and so little time/money. :)

http://www.theplatform.net/2015/05/28/the-other-cray-launche...

TrevorJ2• 11 years ago

What are the advantages of an FPGA in say, my PC? Because it sounds sexy as hell.

nickpsecurity12• 11 years ago

In lay terms, an FPGA is a chip that rewrites itself to be customized for a given use (or uses). Can rewrite themselves as many times as needed and very fast, too. Flexibility means more price, more watts, and less performance than truly custom chip. Yet, having custom circuits for the job can make an application SCREAM with performance. Here's some concepts for you.

1. Compression, encryption, etc that's many times faster (50x on some algorithms).

2. Do high-end streaming workloads (eg HD video, NIDS) on embedded hardware with hardly any watts.

3. Put specialized audio, AI, whatever engines in the FPGA for video games that take it to the next level with a whole CPU left for main game logic.

4. Implement a concurrent, hardware, garbage collector to write your whole OS in memory-safe language and not have freezes due to GC.

5. Use onboard I/O, often many lanes at Gbps, to get crazy throughput on any number of disk, networking, wireless, etc use-cases.

6. Use custom I/O for real-time applications.

7. Simulate other forms of hardware on the FPGA for personal learning or product development. Can deploy it in production on FPGA boards later.

8. Forget software emulators: build the hardware itself on the FPGA and have accurate simulation.

9. Cutting edge techniques do something similar with mockups of normal hardware which are modified to spot the exact time and place certain bugs happen. Then you can see everything from the input that caused it to the internal state of the processor. And fix it.

10. My use-case: processors modified to prevent code injection or data leaks to run applications that hackers can't hit. Altera's I'd use for prototyping then put them on anti-fuse FPGA's: write-once FPGA's that blow circuits intentionally to prevent attackers or glitches from modifying the system's logic. ROP that, bitches!

In short, you can use FPGA's for anything you can use a custom circuit for. They'll just be a bit weaker and usually depend on a host system to set them up. Common case is to have main CPU do most of the work with FPGA's accelerating it or handling interfaces (I/O) in a way they're better at. I'd say Google on FPGA hobby projects, use cases, "applications," etc to see the $3+ billion worth of uses for them. In case you're not drooling, here's a startup that's currently the top performer:

http://www.achronix.com/products/speedster22ihd.html

That joker has over a Gigahertz speed, 6 DDR3 lanes, up to 64 lanes of 12.75Gbps serial I/O, up to 16 of 28Gbps serial I/O, up to 400Gbps Ethernet, 400Gbps Interlaken (datacenter thing), and 2 PCI/Express controllers. Add 1.7 million LUTS for custom logic w/ 138 Mbits of registers or cache... noting that one of those mighty Oracle SPARC T1 processors only needs about 400,000 LUTS... to get a beast of a machine. Those are $10,000 unsurprisingly. Yet, even units that are several hundred dollars can do a hell of a lot and Altera on Intel's process node will do more.

I agree with another commenter that we'll see them in servers and datacenters first. The reason is that they'll have to charge more to recoup the initial cost of making them. Chips aint cheap: probably $5-10+ million per silicon test on Intel's node with mistakes requiring you to spend again. Tools to reduce that start at $1+ million a seat. Good thing FPGA's don't cost all that and have free/cheap synthesis tools. ;)

whazor• 11 years ago

I think the current techniques are becoming too complicated and Intel is now fully going to focus on EUV. The new EUV machines are reaching 70% availability on average, according to the producer ASML[1].

[1] http://www.asml.com/asml/show.do?lang=JA&ctx=5869&rid=52080

RockyMcNuts• 11 years ago

Kind of wondering what this means relative to competitors.

Intel is at 14nm now since 2014 and Samsung recently got to 14nm in Galaxy S6? And Samsung and TSMC have similar roadmaps for 10nm? So conceivably others might be catching up to Intel in fab? Say it ain't so? (I'm asking because I don't follow these things closely but that was the picture I got.)

If Intel doesn't maintain their big edge in fab I'm not sure they can charge the kind of premium they have been. 64-bit ARM is going to start looking mighty attractive for a lot of use cases.

amaranth• 11 years ago

Samsung's 14nm isn't as dense as Intel's because it's sort of a hybrid of a 20nm process and a 14nm one. TSMC's 16nm is apparently just their 20nm process but with FinFETs so will be the least dense of the three. I suspect their 10nm will also end up less dense than what Intel puts out but we'll have to wait and see on that.

As far as timetables for production, recent rumors put TSMC's 10nm plans at 2017 as well, delayed from their original Q4 2016 goal. Haven't see anything about delays on Samsung's side so they might actually get there first.

Intel delays chip-making changes

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