craigjb

We’re at approximately where PCB pricing was 20 years ago, which _is_ a big deal: https://wafer.space

Apple has not shipped an InFO-PoP with side-by-side integrated die yet. This is expected to be the first one, using RDLs for the die-to-die interconnect (so different than M-Ultra series that uses silicon bridges).

Applied Materials, Lam Research, and KLA are all U.S. companies. ASML supplies lithography, but hundreds of other tools come from these companies.

The terms to search for are fan-out wafer level packaging (FOWLP) and TSMC InFO. The chiplets come from different wafers and are reconstituted into a molded plastic wafer, allowing multiple die side-by-side. Then multiple layers of wires are built on top, terminating in a BGA.

7nm for Achronix

https://www.achronix.com/product/speedster7t-fpgas

Equipment for ion implantation already includes mini accelerators [1] [2]. The semiconductor equipment industry in general has many machines that feel like they came out of a physics lab into a semi fab. For example, plasma dry-etching or deep-reactive ion etching. EUV litho is just one of many very interesting problems--currently the bottleneck so it's talked about a lot.

[1] https://en.wikipedia.org/wiki/Ion_implantation [2] https://www.axcelis.com/products/purion-xe-series-high-energ...

edit: add link to cool ion implanter machine pics

You also need hundreds of other machines from Applied Materials, KLA Tencor, Lam Research, Tokyo Electron, etc. Then, years of process development R&D: what temperature do we bake this layer at, how long, what profile, what atmosphere in the tool… Every process step has a large parameter set to optimize. Creating a process is a painstaking many many variable optimization slog.

Just wanted to add that since I see people only mention ASML often here. They are very important, but there is so much more to TSMC’s success.

You are absolutely correct that design costs swamp mask costs by far. For 7 nm, it costs more than $271 million for design alone (EDA, verification, synthesis, layout, sign-off, etc) [1], and that’s a cheaper one. Industry reports say $650-810 million for a big 5 nm chip.

[1] https://semiengineering.com/racing-to-107nm/

I built the Gameslab around this concept, but haven’t worked on it much lately.

https://craigjb.com/2019/11/26/gameslab-overview/

Keep in mind, a semiconductor fab has hundreds of other machines and equipment involved, and US companies are some of the biggest suppliers (Applied Materials, Lam Research, KLA-Tencor--all multi-billion dollar companies).

Lithography is definitely key, but all the equipment and process must work together.

TSMC's plans for Arizona have been increased to start with 100k per month with future phases up to 200k [1]

[1] https://technosports.co.in/2021/03/03/tsmc-to-build-5nm-plan...

The ASML lithography machine is just one, very important, machine out of many dozens. A semiconductor fab process involves 100s-1000s of process steps each with dozens to hundreds of parameters. For example, something as simple as rinsing a wafer after an etch step:

- How long to rinse

- What to rinse with (DI water, solvent, etc)

- What temperature to rinse at

- Should the temperature change over time?

- Agitated vs. non-agitated

It may sound small, but a bad rinse process will tank yields and make the whole process fail.

In a huge semiconductor company like Intel or TSMC, multiple process engineers specialize on each one of these steps out of hundreds. These are truly massive undertakings.

Microchip has the product for you then! Well, the RiscV part anyway. https://www.microsemi.com/product-directory/soc-fpgas/5498-p...

The biggest impact for me I think is the lack of ability to export STEP for KiCad 3D models.

I actually have to disagree. I think it really depends on who you follow. For a long time I didn't use twitter at all, but I've recently become active.

The hardware hacker community (think Hackaday types) on Twitter is pretty awesome and a lot of fun to follow.

Stuff like the below comes through all the time, and the discussions with people making things are great.

https://twitter.com/MrRobotBadge/status/1212038632246251520 https://twitter.com/johndmcmaster/status/1211923709910376449 https://twitter.com/mifune/status/1168604582748073986

Thanks Chris! I didn't know you hang out on HN too :P

You're slowly becoming a software guy after all...

Yeah! Embedded Rust on STM32* right now is pretty good! A lot of consolidation has happened in the device crates and HAL crates recently, so I'm adjusting a bit. But, it's looking good.

I'm actually working on a post about restarting my firmware using the latest and greatest (I started working on this firmware over a year ago).

I used the RFTM real-time OS (RTOS) because it's super light-weight and handy for checking at compile time that my interrupt handlers don't cause conflicts. It's really a nice framework for any event-based firmware (a big chunk).

Thanks! I did a video talking about the case a bit more: https://craigjb.com/2019/12/06/gameslab-case/

I had it fabricated for me by a company by Front Panel Express. In a DIY audiophile forum I saw people using them, and if they're good enough for audiophile gear, probably good enough for me :P

Yeah, Rust is great! I've used it on several production projects for work, but not for extensive embedded work before this. Embedded Rust is getting better and better!

Shout out to the Real Time For the Masses project (it's an RTOS) I used: https://github.com/rtfm-rs/cortex-m-rtfm

Thanks! There was definitely a lot of learning involved--I wrote up some here: https://craigjb.com/2019/12/04/gameslab-fails/

To be honest, I really don't know a good KiCad tutorial. I kind of just banged myself against it until I learned. But, I had previous experience with Eagle, Altium, and Cadence Allegro.

Das U-Boot is the embedded bootloader and is pretty standard for embedded ARM systems (and others! https://github.com/u-boot/u-boot/tree/master/arch).

On a dev-board prototype before, I had also used Buildroot (https://buildroot.org) to create the minimal root filesystem image. This time around, I decided to use Debian since it makes installing packages I want much easier. For example, I can just apt-get install the USB wifi firmware packages instead of hunting them down and including in a manually generated image. It's still using a custom compiled kernel though, since I have custom drivers for things like the graphics hardware.

I'm trying to use Rust for as much as possible (I like Rust a lot). The STM32L0 runs rust, I bodged together a framebuffer driver in Rust, and the games in userspace are also in Rust. I'll post about the Rust framebuffer driver at some point.

The ZipCPU tutorials section is also great! They include verilog, using verilator (for simulation), and formal verification. And, personally, I think learning formal verification early is great, since it will probably be used more and more.

It's verilog, but you're going to have to learn some anyway. All of the new-generation HDLs compile down to verilog, which then goes into the various synthesis tools.

https://zipcpu.com/tutorial/

I've seen a split. Some people are looking for CPU acceleration. Others say Zynq effectively covers the case where FPGA designs include a soft-core anyway for high-level control, so why not make it a hard block.

Yeah, I was going to mention the PS3 too. It was the most unique hardware of the generation and definitely took the longest for devs to adjust to and learn to leverage fully.

Thanks!

I actually didn't originally intend it to be for retro game emulation, more for experimenting with custom hardware for each game and with 3D acceleration hardware. But, the idea of putting retro emulators in the FPGA fabric is so easy.

In fact, over the holidays, I'm working on porting some of the MiSTer FPGA retro emulators to the Gameslab: https://github.com/MiSTer-devel/Main_MiSTer/wiki

I don't think 5W is too far off from what this thing draws under load. I have a 10,000mAh ~4.2V battery in it, and I get about 10 hours of life. The battery is clunky, 9.6mm thick, since it was originally intended for external phone battery packs.

Thanks! I always recommend getting hands-on for learning more about FPGAs. FPGA boards are cheaper than ever, and you have all different ones now. I'd say get a Lattice ECP5 based board (like this year's Hackaday Supercon badge). The open-source symbiflow toolchain works for these (Xilinx 7-series will be soon!).

With regard to Verilog/VHDL, you'll have to learn at least verilog at some point, but I stay away as much as I can. SpinalHDL (based on Scala) is my goto. Some people like the Python based ones like migen, but I like me some strong typing.

I have a couple of blog posts about starting to put together a Gameboy CPU on craigjb.com (not finished yet).

I didn’t phrase that well. I meant that the wafer wafer and panel level embedded technologies embedded the silicon die inside of cheaper epoxy, instead of building expensive silicon interconnect to integrate them on. They basically make a plastic wafer with a bunch of die in it. Then interconnect is built up on that.

Edit: the links below show solder balls. Today this technology is used for packaging, and has been used on chips in phones for years now. In the near future, we should be able to embed or surface mount passives and mechanical components, so maybe we don’t need the PCB.

https://www.semanticscholar.org/paper/3D-eWLB-%28embedded-wa...

https://www.semanticscholar.org/paper/Latest-material-techno...

Package on Package has many downsides though:

- The interconnect pitch is huge, 0.3mm-0.4mm. HBM memories have 1000s of I/Os

- The inductance of the solder balls and the impedance discontinuities in the path mean the logic below still has to have big energy-hungry I/O drivers

- If you want to stack more than one die, you need something expensive like through silicon vias (TSV)

I think the embedded wafer level or "panel" level packaging technologies are the mid-ground. These technologies don't use expensive silicon, and instead surround the die with cheaper epoxy. Then the interconnects are built on top of that, and can connect multiple die together. Yield and interconnect pitch are the big issues here though, and that's why I think you're right, that we will see SoCs or mobile systems first, not whole motherboards.

With that said, some of these technologies can have a layer of surface mount pads on top. So you have a substrate of epoxy with all your chips and interconnects embedded in it, and then surface mount parts on top. For example, passives, connectors, etc. It would look almost like a motherboard, but with all the chips inside. Of course, for cost and yield reasons, this will be for mobile devices only at first.

It's been fun to see Dr. Subu present this concept and prototypes at several conferences, and the level of integration possible is absolutely insane. I think the industry is definitely moving toward chiplets, such as the latest AMD release.

I definitely think we will see more chiplets and more standardization on interfaces between chiplets. The focus will be on how to minimize energy per bit transferred (a big topic in Subu's talks) and how to minimize the die area used for inter-chiplet communication. In monolithic silicon, you don't have to think about die area, since your parallel wires between sections might just need a register or two along the way. With chiplets, you typically can't run wires at that density yet, so you still have some serialization/deserialization hardware. But, since it's not crossing multiple high inductance solder balls and PCB traces, you can get away with less. Hopefully also you can get away without area-intensive resynchronization, PLLS, etc.

I think it will definitely be awhile before this kind of integration is used outside of niche cases though. The costs are just insane. You have to pre-test all manufactured chiplets before integration, and that test engineering is nothing to sneeze at. If you don't then you have all kinds of commercials issues about who is liable for the $500k prototype one bad chip broke.

On the bright side, I see the chiplet approach benefitting other integration technologies. For example, wafer level and panel level embedded packaging technologies can be used for 1-2um interconnects now. You won't get a wafer sized system out of it with any kind of yield, but it's probably the direction mobile chips and wearables will go.

Anyway, disorganized info-dump over.