Analyzing Modern Nvidia GPU Cores

https://arxiv.org/abs/2503.20481

by mfiguiere • 1 year ago

178 37 1 year ago

winwang4• 1 year ago

I hope this can help shed the misconception that GPUs are only good at linear algebra and FP arithmetic, which I've been hearing a whole lot!

Edit: learned a bunch, but the "uniform" registers and 64-bit (memory) performance are some easy standouts.

remcob• 1 year ago

It’s well known GPUs are good at cryptography. Starting with hash functions (e.g. crypto mining) but also zero knowledge proofs and multi party computation.

saagarjha• 1 year ago

They're not particularly good at cryptography, but they are good at highly parallel tasks like trying a bunch of hashes.

qwertox• 1 year ago

Wasn't it well known that CUDA cores are programmable cores?

winwang4• 1 year ago

Haha, if you're the type to toss out the phrase "well known", then yes!

YetAnotherNick2• 1 year ago

In a sense, GPUs are only great at matrix-matrix multiplication. For anything else you would only get 7% of the FLOPs/s compared to it(989 vs 67 TFLOP/s for H100)[1].

[1] https://www.nvidia.com/en-in/data-center/h100/

winwang4• 1 year ago

lol, I haven't thought about it like that, true. though of course, I mean compared to CPUs :P

I try and use tensor cores for non-obvious things every now and then. The most promising so far seems to be for linear arithmetic in Datalog, but that's just matrix-vector/gemv

cma2• 1 year ago

That link says "* With sparsity". For extremely sparse matrixes you can get more than 989 TFLOPS on CPU, if we're counting elided operations in TFLOPS.

randomgermanguy• 1 year ago

Funnily, they're far from being optimal for GEMM ops (especially in terms of power consumption).

For GEMM you need to visit each row/vec n-times so theres a bunch of data-reuse going on, which isn't optimal for GPUs since you can't keep that all so close to your processing-units. And while the tensor-cores kinda implement this i think they don't quite scale up to a full sized systolic array, which is you would want for larger matrix multiplications.

Also just a simpler view: with GPUs most of their silicon is spent NOT tensor-core, so just from that you know its not optimal i guess.

Just referring to that FLOP/s number doesn't really mean much nowadays with tensor-cores and sparsity.

In my eyes the big win of GPUs are that not only are they pretty good at GEMMs but also really good at a lot of other easily parallelizable tasks PLUS they're comparatively easy to program ^^

dist-epoch4• 1 year ago

From your comment I've learned that you never did GPU graphical programming :)

"uniform registers" exist for about 20 years now.

rnrn• 1 year ago

I think you are confusing uniform registers with the uniform keyword in RSL / GLSL / HLSL?

maybe some vendors have had an equivalent to uniform registers for 20 years, but per the articles’ references they are new in nvidia GPUs in turing (2018)

pjc502• 1 year ago

I didn't get that at all - to me this looks like a very smart investigation into instruction latency and the precise mechanics of out-of-order execution (no reference made to speculative or branch prediction, though?) without looking at what the instructions do in detail.

GPUs can certainly do bulk integer arithmetic but most use cases prefer FP. Maybe for DSP fixed-point is ideal.

gmays• 1 year ago

The special sauce:

"GPUs leverage hardware-compiler techniques where the compiler guides hardware during execution."

kookamamie4• 1 year ago

NVIDIA RTX A6000

Unfortunately that's already behind the latest GPU by two generations. You'd have these after A6000: 6000 Ada, Pro 6000.

flowerthoughts• 1 year ago

It's a major step forward compared to 2006.

A6000 was released in 2020: https://www.techpowerup.com/gpu-specs/rtx-a6000.c3686

KeplerBoy• 1 year ago

Nvidia's Quadro naming scheme really is bad these days, isn't it?

I bet there are plenty of papers out there claiming to have used a RTX 6000 instead of a RTX 6000 Ada gen.

kookamamie4• 1 year ago

The naming scheme is horrible, to be quite frank.

To understand this, consider these names in the order of release time: Quadro RTX 6000, RTX A6000, RTX 6000 Ada, RTX Pro 6000, RTX Pro 6000 Max-Q.

pjmlp2• 1 year ago

Still better than most folks have access to.

I bet I can do more CUDA with my lame GeForce MX 150 from 2017, than what most people can reach for to do ROCm, and that is how NVidia keeps being ahead.

kookamamie4• 1 year ago

Yeah, kind of. I have an 6000 Ada and 5090 here.

gitroom• 1 year ago

Haha honestly I always thought GPUs were mostly number crunchers, but there's way more under the hood than I realized. Wondering now if anyone really gets the full potential of these cores, or if we're all just scratching the surface most days?

Dlemo• 1 year ago

There are very good performance tools for GPUs.

I don't think GPU utilization is a real bottleneck in most cases.

dist-epoch4• 1 year ago

Yet DeepSeek managed to get huge improvement by optimizing GPU code.

nabla93• 1 year ago

Overall, we can conclude that GPUs are hardware-compiler codesign where the compiler guides the hardware in handling dependencies and introduces hints that can improve performance and energy.

New architectures rely on the compiler to handle register data dependencies, and controlling register file cache allocation policy.

dist-epoch4• 1 year ago

This is an age-old idea, RISC compilers were supposed to do this too, the mythical "sufficiently smart compiler"

https://wiki.c2.com/?SufficientlySmartCompiler

MindSpunk• 1 year ago

It's not so much about having a "sufficiently smart compiler" in the case of GPUs doing compiler assisted scheduling. It's about not having to implement that logic in hardware at all. The more smarts they push into the core hardware, the more silicon each core needs, the less cores you can fit, and more power you spend on figuring out what to run rather than crunching numbers.

Doing the work in the compiler may produce less optimal scheduling than what is theoretically possible, but with the number of "cores" in a GPU you would spend a lot of power doing it in hardware for each one.

nabla93• 1 year ago

RISC woks well with compilers (ARM, RISC-V), they don't require mythical compilers, just standard good ones.

You are probably thinking VLIW like Intels Itanium, and Transmeta. Those architectures required really smart compiler for scheduling and it was a bust.

Nvidia GPU's need smart compiler and it works because the task is limited to optimizing numerical pipelines that are 99% matrix multiplication, dot products. The data movement is more predicable. Compilers know how the data will be used and know how to schedule.

Analyzing Modern Nvidia GPU Cores

Related Stories