rnrn

looks like a bunch of boring desks for software developers, i don't see any electrical or computer engineers

For example, they invented the .eh_frame walking technique to get stack traces from binaries without frame pointers enabled.

This is not an accurate summary of what they developed.

Using .eh_frame to unwind stacks without frame pointers is not novel - it is exactly what it is for and perf has had an implementation doing it since ~2010. The problem is the kernel support for this was repeatedly rejected so the kernel samples kilobytes of stack and then userspace does the unwind

What they developed is an implementation of unwinding from an eBPF program running in the kernel using data from eh_frame.

No, wrong decade and wrong split - the test & measurement equipment and scientific equipment was long gone from HP at the time of the HP -> HP inc + HPE split. It ended up in Agilent (1999) and from there Keysight.

HP semiconductors went HP -> Agilent -> Avago, now broadcom.

How do get the weights for the right set of experts for a given batch of tokens into fast memory at the right time?

The activated experts is only available after routing, at which point you need the weights immediately and will have very poor performance if they are across PCIe

Why is there a new kernel driver here at all? It appears that all it does it allocate system RAM (“DDR4”) and export it as a dmabuf for import to cuda as mapped external memory. Then a userspace shim hijacks APIs to use that if gpu memory is full. cuda already supports allocating mapped system memory, so AFAICT this could be implemented in the userspace shim with no new kernel driver.

Also as other commenters have mentioned, redirecting allocations to managed memory would also enable similar oversubscription

And the hijack approach only makes sense for making apps have this behavior with no changes, and could be done with minor app changes (e.g. PyTorch has a pluggable allocator interface). App changes also enable intentionally placing specific allocations.

My impression is that this is vibe from beginning to end, starting from a design that only makes sense if you are hallucinating

This is not about reclaiming memory by swapping the contents out to disk. It is about killing processes due to having overcommitted beyond the available memory plus swap space. The processes thrown out of the plane (targeted by the OOM killer) cannot be resurrected

It’s not a cargo cult if the actions directly cause cargo to arrive based on well understood mechanics.

Regardless of whether it would be better in some situations to align to 128 bytes, 64 bytes really is the cache line size on all common x86 cpus and it is a good idea to avoid threads modifying the same cacheline.

even on x86 on recent server CPUs, cache-coherency protocols may be operating at a different granularity than the cache line size. A typical case with new Intel server CPUs is operating at the granularity of 2 consecutive cache lines

I don’t think it is accurate that Intel CPUs use 2 cache lines / 128 bytes as the coherency protocol granule.

Yes, there can be additional destructive interference effects at that granularity, but that’s due to prefetching (of two cachelines with coherency managed independently) rather than having coherency operating on one 128 byte granule

AFAIK 64 bytes is still the correct granule for avoiding false sharing, with two cores modifying two consecutive cachelines having way less destructive interference than two cores modifying one cacheline.

Do you use some old version of iTunes to put music on it or are there other tools with better support for old iPods?

This was in the “truth” posted by Trump on his social media announcing the deal:

It is my Great Honor to report that the United States of America now fully owns and controls 10% of INTEL, a Great American Company that has an even more incredible future. I negotiated this Deal with Lip-Bu Tan, the Highly Respected Chief Executive Officer of the Company. The United States paid nothing for these Shares, and the Shares are now valued at approximately $11 Billion Dollars. This is a great Deal for America and, also, a great Deal for INTEL. Building leading edge Semiconductors and Chips, which is what INTEL does, is fundamental to the future of our Nation. MAKE AMERICA GREAT AGAIN! Thank you for your attention to this matter.

“The United States paid nothing for these Shares”

https://truthsocial.com/@realDonaldTrump/posts/1150744446179...

Are you sure congress didn’t authorize this ? i.e. actually specified that the money could only be used for grants and could not be used for equity purchases?

The Department of Commerce is authorized to provide funding in various forms, including grants, cooperative agreements, loans, and loan guarantees, in exercising its Section 9902 authorities

https://www.congress.gov/crs-product/R47523

AFAICT the relevant section of law says it is up to the Secretary of Commerce to determine the funding type to be used for the semiconductor financial assistance

https://www.congress.gov/116/plaws/publ283/PLAW-116publ283.p...

See my other comment : https://news.ycombinator.com/item?id=44995799

I thought this too, but after reading some of the other comments here I read some of the text of the chips act and the 2021 NDAA (mostly section 9902) and AFAICT Congress appropriated a bunch of money for financial assistance for semiconductor companies and gave the Dept of Commerce the authority to determine the funding type.

That they were grants instead of any other instrument appears to be a Biden Commerce decision, not a congressional one.

I’m no lawyer and could certainly be missing something i the law that says it has to be grants but from what I see it looks like figuring out what to do the the money was pretty much delegated to dept of commerce with limited direction about eligibility and review criteria.

*consummate Vs

This should be made obvious by the fact that both the metal-semiconductor transistor (i.e. MESFET, patent filed on 1925-10-22) and the depletion-mode metal-insulator-semiconductor transistor (i.e. depletion-mode MOSFET, patent filed on 1928-03-28) have been invented at a time when quantum theory was just nascent,

I don't think that makes it obvious at all, given that the none of these invented devices actually worked, and the first working MOSFETs weren't until the late 50s after a research program of a few additional decades by a bunch of solid-state physicists at Bell Labs (who did know and develop quantum theories of solids - Shockley, Bardeen, Brattain - not successful in making a FET -Atalla, Kahng, many others)

"Electrons and Holes in Semiconductors" was published almost a decade before any functional MOSFET was constructed.

For designing MOSFETs, you just need to use classical electrodynamics, together with several functions that provide the semiconductor material characteristics, like intrinsic free carrier concentration as a function of temperature, carrier mobilities as functions of temperature and impurity concentrations (and electric field at high fields), ionization probabilities for impurities, avalanche ionization coefficients, dielectric constants, and a few others.

It sounds like you are describing what's required to parameterize some of the traditional semi-classical models of MOSFETs and understand the operating principles at that level.

but FETs work by bending the energy levels of the conduction band so there needs to be a band to bend, and if there's no band gap at the fermi level you can't have a FET, which makes it seem pretty dependent on quantum effects to me even without going deeper than necessary to understand how it can work.

Maybe one could have been engineered with no idea why silicon has the special material properties that it does and why doping changes those properties but AFAIK it never was, and being able to explain and understand band structure seems pretty important to build a working device.

The NMOS transistors used in the 6502 were quite large and worked on the basis of electrostatic charges ... as opposed to bipolar transistors that are inherently quantum in operation

Forming a conductive channel in silicon in any FET and semiconductivity in general is an inherently quantum effect too, right?

Are these instances actually funded by 2021 IIJA BEAD program?

I don’t think Illinois has actually awarded any of that funding to providers to build anything yet. It looks like the original schedule was to start awarding grants this summer after planning process from 2021-2025.

https://dceo.illinois.gov/broadband/bead.html

removing comment since I regret attempting to engage in this thread

removing comment since I regret attempting to engage in this thread

I think you are confusing uniform registers with the uniform keyword in RSL / GLSL / HLSL?

maybe some vendors have had an equivalent to uniform registers for 20 years, but per the articles’ references they are new in nvidia GPUs in turing (2018)

I don’t think x86 as an ISA is necessarily declining much and AMD has products with zen4c / zen5c compact cores intended to compete with Arm server products. AMD doesn’t have to pay licensing / royalties for x86 AFAIK and probably would prefer to keep x86 and not start paying arm and creating any adoption barrier form a change of ISA (however small) if they can make competitive x86 cores.

I assume the question is why AMD is not making EPYC or Ryzen processors with Arm cores for the application processors.

AMD continuing to have the Xilinx line of FPGAs with some Cortex cores and having Arm management cores that run firmware doesn’t really address this.

we could also look to magnetoresistance and go for giant, colossal, extraordinary

it's too bad vLLM and VLM are taken because it would have been nice to recycle the VLSI solution to describing sizes - get to very large language models and leave it at that.

a full duct spinning at 10k rpm seems like it would massively increase stress on the blades

It also meant anyone who actually wanted a CPU core in their design got something that was guaranteed to work and easy to integrate.

in theory only.

caravel had hold time violations and the pin configuration mostly didn’t work for the first 5 or 6 sponsored OpenMPW shuttles.

Since i posted https://news.ycombinator.com/item?id=43124176, they have revised again to acknowledge that many of the other generated kernels are also broken:

Furthermore, we find the system could also find other novel exploits in the benchmark’s tasks

“Novel exploit” is a pretty fancy and generous way of saying that some of the kernels wrote a constant value to the entire output because the evaluation code only tested one set of inputs that can pass if you replace the computation with a memset.

As I write this (after the updates to the evaluation code), https://pub.sakana.ai/ai-cuda-engineer/kernel/2/23/optimize-... is on their top of their list of speedups, with a claim of 128x speed up on a fused 3D convolution + groupnorm + mean.

The generated implementation doesn’t do a convolution.

The 2nd kernel on the leaderboard also appears to be incorrect, with a bunch of dead code computing a convolution and then not using it and writing tanhf(1.0f) * scaling_factor for every output.

Answer: it can’t.

The author has updated the post with corrected AVX measurements, with the original ~340 GB/s revised down to 31.7 GB/s. (Thanks CowFreedom)

But about bandwidth, matrix multiplications happen mostly in cache and that has a lot more bandwidth than RAM. Blocks of the matrix are loaded to cache (explicitly in CUDA) and used multiple times there.

The post is about dot product, not matrix multiply. Dot product has no data reuse

how can the multicore AVX implementation do a dot product (for arrays much larger than cache) at 340 GB/s on a system with RAM bandwidth < 50 GB/s