TSMC 2nm Update: Two Fabs in Construction, One Awaiting Government Approval

https://www.anandtech.com/show/21241/tsmc-2nm-update-two-fabs-in-construction-one-awaiting-government-approval

by ksec • 3 years ago

135 78 3 years ago

That means it should ease demand for the 3nm node so we can see more non-Apple chips on it?

I'm just curious where'd does TSMC find free real estate in Taiwan for so many fabs. At this rate Taiwan will be all TSMC fabs.

arccy• 3 years ago

for the amount of money they make in the relatively small footprint, sacrificing a scrap of farmland is always worth it

FirmwareBurner2• 3 years ago

You need a lot more than scrap farmland. The amount of water semi fabs consume is insane, and Taiwan doesn't have abundant clean water sources.

creer2• 3 years ago

At the same time, you would think by now there would be better planning - preserving useful farming soil for farming. But yeah, the difference is too high for most places to bother. In any country I know of.

It's fair also that some farming activity is not very compatible with high human density nearby, such as spraying and dust. So it's hard to intersperse high rises with production farmland.

ytch• 3 years ago

https://focustaiwan.tw/business/202311100005

At this rate Taiwan will be all TSMC fabs.

It's almost in every big cites, but there are still some regions in Taiwan that don't welcome TSMC to set up factories.

tyingq• 3 years ago

The headline here is verbatim from the story, but reads better as

"TSMC 2nm Update: Two Fabs in Construction, Third Awaiting Government Approval"

ramshanker• 3 years ago

I am surprised with the absence of Cerebrus style x64 or ARM or NVDA GPU chips on the leading nodes.

ksec3• 3 years ago

Providing a little more context before things get blow out of proportion.

This is the first time TSMC has done two large feature set in one node generation. TSMC's N2 will first use gate-all-around (GAA), with an improved N2P coming with BackSide Power Delivery Network (BSPDN).

As with any new large node features, capacity will be constrained, so instead of the usual one additional Fab online per year expansion in leading node, they are bringing online 3 in the space of 2 years. This is also discounting that we dont know the total Wafer output of each Fab. But if we look at the recent Q4 report it does seems HPC ( or likely AI ) has infinite appetite for wafer capacity. So I wont be surprised if it is indeed a substantial increase in wafer capacity on leading node.

We will know ( or we can infer it ) once they start doing 2nm revenue reporting. TSMC tends to be very transparent with these sort of things. Something I hope Intel IFS will copy as well.

wslh3• 3 years ago

Could you please elaborate for the general HN public what TSMC is doing and how they are advancing too fast while Intel (also AMD?) are "stagnated"? I am not talking about bashing Intel but it seems there is a lot to talk about TSMC from the science, engineering, and business execution perspectives. It seems like TSMC is playing a complete new game in the chip industry.

cma3• 3 years ago

Engineering wise Intel was part of EUV LLC in the late 90s but sold off their portion later in the 2000s I believe. It was a public/private partnership to develop EUV lithography and is the reason the US is able to dictate EUV machines not go to China.

mschuster91• 3 years ago

Could you please elaborate for the general HN public what TSMC is doing and how they are advancing too fast while Intel (also AMD?) are "stagnated"?

AMD hasn't stagnated, they've made some serious progress in the last years, and they've long ago gone fabless - they spun off GlobalFoundries in 2009, and mostly deal with TSMC. The biggest problem AMD has when compared to anything ARM is the instruction set - x86 carries a crapton of baggage with its 40-ish years of history and backwards compatibility, while ARM is relatively clean.

Intel stagnated because they messed up big with their node shrinking and for inner-political reasons couldn't say they go with TSMC as well so they were stuck with their old nodes.

huijzer• 3 years ago

By "new game" you mean what they have been doing for 30 years?

bee_rider7• 3 years ago

TSMC only does fabrication, no chip design. Pretty much everyone making high-performance parts other than Intel sends uses them, AMD included. This is typically known as the “foundry” business. They are the biggest pure foundry by far, and all of their competition has some downside (Intel and Samsung aren’t pure foundries, you have to compete with their in-house demand, Global Foundries is behind and isn’t competing for the smallest nodes anymore, and SMIC is a state-owned Chinese company and, among the other concerns that brings up, they can’t get access to the latest photolithography machines for geopolitical reasons).

Speaking of politics TSMC, is in a unique geopolitical position. Their government sees being the chip foundry for the whole world as an existential issue. China would like to take over Taiwan for historical reasons, and they can’t possibly build a large enough army to defend themselves against a really motivated full-strength attack. So instead they have put themselves in a position where any attack would be incredibly disruptive to the global economy and anger everybody.

The silicon industry is famous for very long roadmaps, very long investment payback times, cyclic demand, and winner-take-all competition. It is brutal. TSMC, serving everyone and with a friendly government at their back, is in a good position to out-endure everyone.

That’s the business part. The science and engineering is over my head, and I think sort of hard to talk about. Each node is a new engineering marvel basically.

Tempest1981• 3 years ago

Asked here recently:

https://news.ycombinator.com/item?id=35665076

blackoil• 3 years ago

Intel plans to launch 20A(~2nm) by end of year or early next year.

agd• 3 years ago

Intel (also AMD?) are "stagnated"

Intel are catching up and will likely launch their 20A node before TSMC 2nm. Intel's 20A also includes gate all around and backside power delivery, so I don't think it's accurate to say Intel are 'stagnated' any more.

ksec3• 3 years ago

Judging from questions like why dont Apple buy TSMC or built their own foundry I would guess a lot more context will be needed and it would be at least a few thousands words if not more.

But to put it short, and one point that is not pointed out enough. TSMC has always been the leading edge foundry for nearly all SemiConductor company apart from Intel and AMD. If you want the most advance third party foundry, you basically only have TSMC to choose from. That has been the case since at least 2008. ( Or arguably a lot longer ). So for pretty much everyone in the industry nothing much has changed. TSMC mapped out their roadmap, speak to a few key client on their needs and capacity, plan their investment and ROI accordingly. The only thing that had changed is that they somehow not only are the leading edge on Foundry services, but also leading in terms All Silicon producer, where Intel used to be the king. So one way to think about it, is that TSMC has been executing like clock work for the past 20+ years. While Intel has multiple minor slip and one major slip in terms of node process, and also completely missed out on Smartphone revolution which provided an additional 2 Billion+ consumer electronics market using silicon chips, and they didn't get to enjoy the amortization over those potential 2 Billions unit volume. Even if they did like the 200M Apple Modem order, they completely failed to plan the CAPEX and OPEX spending and capacity planning. Which was later confirmed Intel's CEO Bob Swan. ( Not his fault. It was all on Brian Krzanich ). So to answer your question. "how they are advancing too fast while Intel (also AMD?) are "stagnated"?"

It was't TSMC moving too fast. It was Intel completely fucked it up. I wrote a lot about how Intel should have done Foundry in 2011 and how they missed everything by 2014. But a lot of these were only obvious now. Some of my comments below from 2016 and 2020.

Edit: That doesn't mean I am negative on current Intel. I was so happy and cried when Pat Gelsinger got back to Intel as CEO. It is a tough battle. But if Pat dont make it work then I doubt anyone else could either.

Copying what I wrote in 2020 [1]

Tl;DR, It is TSMC, not Apple.

I have been thinking starting a blog on the topic considering how often this question keeps popping up. From a very high level overview.

1. Apple is partnering with TSMC. TSMC is now the leader in leading edge semiconductor manufacturing. A title that used to belong to Intel.

2. TSMC is now a generation ahead of Intel, meaning those thermal efficiency you see comes from using a better node. Nothing much to do with ARM or x86.

3. Both ARM and TSMC has dramatically change the Industry, you can now buy Designs / Blueprints from ARM, ( Or any other IP vendors such as Img PowerVR ) and Fab ( meaning producing them ) them with a Foundry.

4. TSMC is a Pure Play Foundry, meaning the Foundry does not produce their own chip and sell in the market to compete with its customers. A Non Pure Play Example would be Samsung or Intel, where Samsung produce their own Mobile SoC Exynos, and Intel with their x86 Chip. If you were Qualcomm producing your chip in Samsung's Fab, you are directly competing with them.

5. Apple now has the volume, or economy of scale to produce CPU themselves. Apple makes more silicon in unit volume than Intel per year.

Another Comments I wrote in 2016 [2]

These process, R&D, process optimization, materials science are all cover by their cost to TSMC / Samsung. Btw TSMC's 2016 Capex ( including R&D ) is now equal to Intel $9.5B. When you consider TSMC is Pure Play and Intel being IDM, this is very significant mile stone.

[1] https://news.ycombinator.com/item?id=23822834

[2] https://news.ycombinator.com/item?id=12947327

sylware• 3 years ago

As you said N2 seems to be some sort of major milestone... and why 3 fabs? Well, I would naively say that will help TSMC production capacity to avoid being "trusted" by a few vendors and let alternatives access state-of-art N2... finally risc-v powerful micro-archs with N2?

hyperthesis2• 3 years ago

Since nm are Now Marketing, unrelated to physical dimension, how consequential is this node shrink? It must have passed some threshold to justify new factories - what was it?

nightski• 3 years ago

Would it make a difference if it was physical dimension? Wouldn't you simply be asking the same question?

ip26• 3 years ago

I have no inside information, but gate-all-around and backside power are both pretty big developments. If you remember the rise of finfet, gate-all-around will probably be a similar step up (maybe slightly smaller). My guess is backside power is the less impactful of the two, and a little less directly quantifiable, but for route-limited designs it should enable 10-20% higher density which reduces cost and improves performance. It may also deliver higher quality power supplies, which improves power efficiency and maximum clock frequency.

It's hard to directly answer "how consequential", but it seems like it could be as significant as the step to TSMC 16nm.

prng20212• 3 years ago

"In July 2022, TSMC announced that its N2 process technology will feature backside power delivery and will offer 10–15% higher performance at iso power or 20–30% lower power at iso performance and over 20% higher transistor density compared to N3E"

https://en.m.wikipedia.org/wiki/2_nm_process

audunw3• 3 years ago

Since nm are Now Marketing, unrelated to physical dimension

That's not entirely true. They might not decrease the minimum gate length, but generally the improvements made when bumping down the "nm" number has been a similar improvement as what making the gate length smaller would have given. So I don't find the numbering as misleading as others think.

It's not like any of us a designing gate cell libraries (well, I have, a very basic one, but I'm guessing most here haven't), and actually care about the gate length.

Using the minimum gate length as a naming scheme was always been a proxy for things chip designers actually care about: logic density, timing, power, etc.

phatfish• 3 years ago

Marketing sure painted themselves into a corner on this one by counting backwards, they only have one generation left before things get weird. Will they use fractions or go negative?

Ciantic• 3 years ago

"it usually builds a new fab to meet demand of its alpha customers and then either adds capacity by upgrading existing fabs or building another facility. With N2 (2nm-class), the company seems to be taking a slightly different approach as it is already constructing two N2-capable fabs and is awaiting for a government approval for the third one."

Customers would probably want to have plants outside of Taiwan, but proactively approving a new plant and starting to build one even before you have customers gives more leverage to Taiwan. This is just as much about Taiwan's security as it's about good business.

samus2• 3 years ago

The fabs don't really have strategic value because the pace of development has slowed down. The fabs are presumably rigged for easy sabotage, so if something... happens to Taiwan, neither China nor the West can make use of them. It would barely affect the state of the art since Samsung is not far behind and Intel will eventually get its sh*t together again. And key parts of the supply chain are in the West, and China's access to it is already restricted.

Edit: they have massive economic value of course, but economic factors alone have rarely prevented conflicts.

Snow_Falls4• 3 years ago

If TMSC fabs go down, the world silicon foundry output would drop by a significant chunk. That could have an effect but the majority of the worlds silicon use is in less advanced nodes which many companies produce, it would slow down the state of the art sure, but it probably not be as catastrophic as some people imagine.

creer2• 3 years ago

It's easy to dismiss economic impact in conflicts. Even the phrasing "economic factors alone have rarely prevented conflicts" is a little glib. US administrations (and all others) have to remember how the Cold War ended; The Oil Shock; the effect of fracking on the viability of action in the middle east (thrown together in one salad :-); the whole point of much conflict in the middle east; the Houthis firing at ships passing by; etc, etc.

So not all conflict is tied-in with economics sure but wouldn't loosing most TSMC production and china-based supply chains be a major shock? For all sides? And as such would be taken into account?

ijhuygft7764• 3 years ago

so, how many nanometers is 2nm?

Snow_Falls4• 3 years ago

If this isnt a joke, 2nm=2 nanometers.

ijhuygft7764• 3 years ago

If this isn't a joke, you are wrong. What a world we live in.

Today, terms such as “2 nanometer” and “3 nanometer” are widely used as shorthand for each new generation of chip, rather than a semiconductor's actual physical dimensions.

Its almost as if we live in 1984 where newspeak goes un-noticed

coltonweaver• 3 years ago

For those unaware, "2nm" is marketing-speak. The actual physical dimensions are 45nm gate pitch and 20nm tightest metal pitch for 2nm.

https://en.wikipedia.org/wiki/2_nm_process

https://www.pcgamesn.com/amd/tsmc-7nm-5nm-and-3nm-are-just-n...

daxfohl• 3 years ago

Oh wow, so a 7 percent improvement, not 50 percent. I'd heard about the disparity, but didn't know it was that big.

apienx• 3 years ago

Reminder that technology nodes (5nm, 2nm, etc.) refer to the smallest feature, not some dimension of the transistor channel. For reference, a silicon atom is 0.21nm.

Snow_Falls4• 3 years ago

They used to refer to the smallest features, but they haven't had any real meaning for a long time now. The names of the nodes don't correspond to any physical feature of the actual transistor anymore.

bee_rider7• 3 years ago

We should really measure this based on density for some basic repeated structure, or something like that. Adder-density or something, haha.

anticensor• 3 years ago

What about the surface area of a basic ALU NAND gate and a basic DRAM cell?

audunw3• 3 years ago

Who cares? It's not like most of us are designing logic gate cells for chips. The transistor dimensions are irrelevant to us.

I really don't understand why this keeps getting brought up. It's not even an interesting fact.

When the chip manufacturing industry started finding other ways to increase logic density, improve timing, reduce power consumption, etc, they just started bumping down the "nm" number to indicate the improved performance, in a similar way as reducing the transistor gate length would have done before. Simple as that.

stephenitis• 3 years ago

Did ASML advance the technologies for this node?

Who reserved all the expected output I wonder.

nabla9• 3 years ago

That must be something like 40-50 billion in investment.

amelius2• 3 years ago

Does anyone know of a good book on semiconductor physics and manufacturing that doesn't read like it was written in the 70s?

gowings97• 3 years ago

"But if we look at the recent Q4 report it does seems HPC ( or likely AI ) has infinite appetite for wafer capacity."

Famous last words

TSMC 2nm Update: Two Fabs in Construction, One Awaiting Government Approval

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