TSMC to Mass Produce Breakthrough 2nm Mbcfet Transistors in 2024

https://wccftech.com/ssmc-mass-produce-2nm-2024/

by Nokinside • 6 years ago

110 65 6 years ago

Alopis• 6 years ago

With this news, how much of a lead do they have over Intel now? When is Intel realistically going to ship their next node? Or is it all still perpetually delayed with no end in sight?

j4nt4b• 6 years ago

So is it safe to assume that Apple will book 100% of the first production runs for this new process as well?

vbezhenar2• 6 years ago

I think it depends on price. At some point chips will cost too much for consumer electronics. You wouldn't want to buy iPhone with $1000 CPU.

throwaway4good2• 6 years ago

A mass volume product like an iPhone is the only thing that generates enough money to sponsor this form of development.

epicureanideal• 6 years ago

Sign me up!

mschuster91• 6 years ago

You wouldn't want to buy iPhone with $1000 CPU.

1.000 US$ no, but... I would not put it past Apple to make a literal system on chip. Like, one chip with everything on one die stack: CPU, GPU, RAM, cell modem, voltage regulators... the only external components would be ports and whatever cannot be reasonably expressed on a silicon die (e.g. coils for voltage regulators).

AgloeDreams2• 6 years ago

Chips don't really work like that. 99% of the cost is in R&D and factory development then the cost per chip is pretty low, you just have to average in the R&D cost right? Apple sells ~ 200M units every year and prior developments get rolled into low cost products. Each new process probably leads Apple to make at least 500M devices. At scale you can spend 10s of billions on R&D and be spending less than $15-25 per chip.

zamalek• 6 years ago

Price depends on yields, and 90% is pretty damned good.

ksec4• 6 years ago

It depends on a lot of factors, but mainly cost and yield.

Example; Apple didn't use any 7nm EUV variant in A12/A13. While Huawei used it for their SoC. Having said that MBCFET, or more commonly known as GAA was originally scheduled for 3nm in 2022, so giving another 2 year to bake should help.

So yes, if everything were executed to absolute perfection, then we should see a 2nm Apple Silicon in 2024.

Note: While Wccftech has gotten a lot better in the recent 12 months or so, I still wouldn't put them into reliable and trusted source. It is good for rumours and entertainment, but that is about it. ( Personally I would rather not have it appear on HN )

throwaway4good2• 6 years ago

Is TSMC the only who is close to doing this?

What about Samsung or Intel? Or research labs that do smaller runs?

vbezhenar2• 6 years ago

I think that Intel is one step behind. They'll likely produce 7nm in 2024 which should be comparable with TSMC 5nm. But TSMC 5nm already available for Apple.

derision• 6 years ago

Intel is more like 3 steps behind, one of their shoes is missing and the other is missing laces

AgloeDreams2• 6 years ago

And that is even a bit of a high risk guess, probably closer to 2025. But yeah, pretty much. Is Intel even looking into Mbcfet?

gimmeThaBeet2• 6 years ago

FWIW I thought Samsung trademarked the name MBCFET. Not saying that is in fact worth much, just that I know for a fact Samsung has been concrete about when this is going to be a process customers can use.

On paper I don't think it's risky to say everyone is looking at GAAFETs and MBCFETs, they're the evolution of finFETs (okay, we have the fin, what about more than one fin? Okay, how about the channel is surrounded by the gate (Gate-All-Around)?) How far along is everyone to making them commercially available with good yields, ¯\_(ツ)_/¯.

I think the surprising thing to me was TSMC has thus far (as of like a month ago) been of the mind "nah, finFETs are fine". But keep in mind, that was for their 3nm node, which this isn't.

https://www.anandtech.com/show/16041/where-are-my-gaafets-ts...

ksec4• 6 years ago

That is certainly not true.

TSMC has always had a conservative culture. They dont aim at x% of improvement per process node like Intel. GAA for 3nm has long been known to be not ready for 2022. They actually mentioned this in 2019. But it was only confirmed later at a conference that Anandtech picked it up. Mainstream media being an echo chamber decide to copy each other and the news spread like wild fire.

So it was only logical to push those improvements to 2nm.

jmt_2• 6 years ago

Can someone ELI5 how TSMC is able to produce sub-7nm chips? I know quantum tunneling and the like becomes an issue at this size. I don't have a great physics background so I'm struggling to find a simple enough explanation for how they are dealing with this. Is it not as big a deal as I may think?

vkou• 6 years ago

It's easy. You take a very small number, add the letters 'nm' to it, and then start sending out press-releases to the major media outlets.

That number has nearly zero bearing on the actual physical sizes of the chip's components.

The only people who know about the exact dimensions are the firms placing manufacturing contracts with TSMC.

vmception• 6 years ago

You get it

gruez• 6 years ago

That number has nearly zero bearing on the actual physical sizes of the chip's components.

AFAIK the reason behind this madness is that the number previously did correspond to feature size, but then they discovered methods of increasing transistor density without decreasing the size of the components. Since the feature size was used in marketing as a proxy for transistor density, they felt it was ultimately justified to decrease the number. After all, if your enhanced 32nm process provided the same transistor density as your competitor's 22nm process, why shouldn't you market your process as "22nm"?

nicoburns• 6 years ago

To make an analogy: I think a good way to think about it is that the 7nm node doesn't actually produce chips with 7nm features, it uses a "knife" (actually it's a lithography process) which is able to cut things as small as 7nm . That enables it to be more precise than a bigger "knife" so even though the size of the chip features is >7nm they are still able to be smaller than features cut with a 10nm "knife".

I don't actually know anything about chip production. But that's what I've picked up from HN.

tux3• 6 years ago

One thing people are trying to convery every time this question comes up is that "7nm" is really just a marketing number, it's not tied to any particular physical dimension, and it's not how small the knife is able to cut.

The knife does get better, it's just not something that the Xnm node names measure directly.

marcosdumay2• 6 years ago

That's kinda the idea. There are also several different layers each with its own resolution.

Also, well, that number isn't really the actual resolution of the finest layer, but is some "marketing processed" message that should give you an idea of the chips performance. It used to have the meaning you stated, but things changed a while ago.

Nokinside2• 6 years ago

The number 7nm 5nm etc. ceased to refer anything physical after the technology moved on from planar transistors. Now it's just a commercial name for a generation.

The most important dimensions are the gate pitch and metal pitch. For TSMC's 7nm process they are something like 60 and 40 nm and go down in the future to something like 30 nm and 20 nm in the 2nm process. Fin width might be the closest thing to commercial name.

They are not even comparable across companies. For example, TSMC 7nm process technology has 91 MTr/mm², Intel's 10 nm prosess technology has 100 MTr/mm². Samsung 10nm has 52 MTr/mm². (MTr/mm² refers to millions of transistors per mm²).

swiley2• 6 years ago

That's interesting, I saw a hobbyist photo lithography setup the other year that was able to etch metal with a resolution of 20nm.

tiffanyh2• 6 years ago

What's the MTr/mm2 for TSMC 5nm? 2nm?

EDIT: looks like 173M for 5nm. https://en.m.wikipedia.org/wiki/5_nm_process

jmt_2• 6 years ago

Very interesting, thank you. So we're basically not nearly as close to "true" 7nm as I thought? Do companies like TSMC already have a plan as to how to deal with "true" 7nm or is a lot more research still needed?

AareyBaba• 6 years ago

For perspective, 2nm is approximately how much your fingernail grows in the time it took to read this sentence.

(3.47mm per month)/(30 * 24 * 60 * 60 seconds) = 1.33nm/second

robert_dipaolo• 6 years ago

der8auer recently did a 3 part video on YouTube where he cut up AMD and Intel chips and looked at the transistors with an electron microscope. It sheads some light on meaning (or non-meaning) of the node names. Is also really interesting;

https://youtu.be/uEMDkbF3hu0 https://youtu.be/uXu_1zXOZdY https://youtu.be/_wAeL3f3iV4

agumonkey2• 6 years ago

With all the electronics and physics chans I binge on youtube I'm surprised this one never hit the suggestion fan, it's utterly fascinating

1000100_1000101• 6 years ago

Not the explanation you're looking for, but the CTO at TSMC co-invented the modern FinFET transistor. They've probably good a really good grasp on what issues block development of smaller features, and know how to find ways around those limits.

https://spectrum.ieee.org/semiconductors/devices/how-the-fat...

egsmi4• 6 years ago

He also wrote an excellent introduction to semiconductor physics textbook, that Berkeley hosts for free!

https://www.chu.berkeley.edu/modern-semiconductor-devices-fo...

imtringued2• 6 years ago

The nm process numbers refer to the necessary dimensions of a theoretical planar transistor to achieve the same density as this process. Planar transistors haven't been used for at least a decade. To make matters worse there is no standardized planar transistor design so ultimately you cannot derive any meaning from these numbers other than as a fancy version number that tells you which process is newer. As many others have commented: It's much better to just look at overall transistor density.

FinFET and GAA (gate all around) are 3d transistor designs. Therefore you get impossible and purely theoretical planar numbers.

rasz• 6 years ago

der8auer "14nm and 7nm are NOT what you think it is - Visiting Tescan" https://www.youtube.com/watch?v=1kQUXpZpLXI

for reference "TESCAN is a leading global producer and supplier of scanning electron microscopes, focused ion beam scanning electron microscopes and micro-CT solutions."

tmd83• 6 years ago

https://www.youtube.com/watch?v=3otqUu-7WUQ Surprising for the flashy marketing style of the video it really explained to me the difference between FINFET, GAA and MBCFET really well.

Is Samsung and IBM stronger in structural R&D then they are at FABs?

LargoLasskhyfv3• 6 years ago

Yes. That was a good one. Acessible.

TSMC to Mass Produce Breakthrough 2nm Mbcfet Transistors in 2024

Related Stories