SiFive Introduces 7 Series RISC-V Cores with E7, S7 and the U7 Series

https://www.cnx-software.com/2018/11/02/sifive-7-series-risc-v-cores-e76-s76-u74/

by pepsi • 8 years ago

179 47 8 years ago

cnx-software.com

jbeard4• 8 years ago

I am pretty excited about RISC-V. Hoping to see a v8 JavaScript and Node.js port in the future.

thethirdone• 8 years ago

That shouldn't be super hard. I don't think there is much assembly in either. And C can be compiled to RISC-V already.

My only experience porting node was to a specialized ARM system a while ago, so ARM support may have been already built in or things may have changed.

edit: as people have commented, there indeed is a fair amount of arch specific stuff for reference the mips directory https://github.com/v8/v8/tree/master/src/mips64

comex• 8 years ago

V8 has a JIT, which is always going to require work to port to a new architecture. But the new-ish TurboFan backend is supposed to have the architecture-dependent parts relatively well factored out[1], so it's not as hard as it might be.

https://docs.google.com/presentation/d/1_eLlVzcj94_G4r9j9d_L...

Matthias247• 8 years ago

v8 is a JIT compiler. It emits instructions for specific architectures. So even if it's not written in assembly, it has some very architecture specific parts in it.

gnulinux2• 8 years ago

When can I buy an affordable, complete RISC-V computer? I've been long planning to cook my own with FPGA but it seems like soon we'll start getting affordable RISC-V CPUs with other utility support?

antome• 8 years ago

Affordable RISC-V systems will only happen if they reach a comparable level of mass production as proprietary systems. What you will more likely see for now is a gradual increase in the number of components on GPUs, HDDs etc which use RISC-V instead of ARM or something else. The ISA is only a part of the cost equation.

zik• 8 years ago

There are none yet. RISC-V is likely to appear in embedded and mobile devices before a full desktop machine is competitive with Intel processors.

mkl2• 8 years ago

Why not embedded? It seems like that would happen well before full desktop machines and competitive speeds.

mrweasel• 8 years ago

It's most likely going to be like with ARM and be embedded only, sadly. There's a large number of us, not large enough though, that want a standard ATX motherboard, with PCI-Express and an ARM, RISC-V or PowerPC processor (well an affordable PowerPC).

qlk1123• 8 years ago

With QEMU you can already do amazing things. Every component required by Linux From Scratch has been stable, and you can get a Fedora/Debian image for that as well.

trasz• 8 years ago

Same with FreeBSD.

gnulinux2• 8 years ago

I know QEMU works, I wrote a small kernel using RISC-V and just want to see it on bare metal.

risky_v• 8 years ago

Some progress reported a few months back https://news.ycombinator.com/item?id=17642872

snvzz2• 8 years ago

Unfortunately with RV64G, not RV64GC (which is targeted by Linux distributions and the BSDs).

Something they can fix, but this iteration's going to be not very convenient because of that.

mcbits• 8 years ago

They sell an Arduino-class device (technically a computer) called the HiFive1 for $59, and there was a crowdfunded SBC called the HiFive Unleashed that was a limited run for $999. Both are about 5-10x too expensive for poor me, but I'm keeping my hopes up for a commodity-priced SBC to replace my laptop when it finally kicks the bucket.

makomk• 8 years ago

I'm not sure how useful one of those would really be, to be honest. There's not really much benefit in terms of openness - even though the architecture is open, these actual implementations are entirely proprietary with license agreements that forbid reverse-engineering. Plus it's just not as widely supported as ARM on the software side right now.

Tor32• 8 years ago

The 'openess' does nothing for end-users, but it makes a difference for chip vendors - they don't have to pay license fees, unlike for ARM.

tyingq• 8 years ago

The LowRisc project seems to have the mission you're looking for:

"What are the goals of the project? To create a fully open SoC and low-cost development board and to support the open-source hardware community. This will involve volume silicon manufacture..."

They have 2 folks with prior experience on the Rpi team. But, it's hard to tell when they might have something ready. http://lowrisc.org

rwmj• 8 years ago

LowRISC 0.6 was just released which finally has support for RV64GC so you can run Fedora & Debian (ie. real distros!) on it. We're discussing on the mailing list how/when to get the kernel and driver changes upstreamed: https://listmaster.pepperfish.net/pipermail/lowrisc-dev-list... https://listmaster.pepperfish.net/pipermail/lowrisc-dev-list...

The upshot of this is you can run lowRISC 0.6 on something like the Nexys 4 DDR (other FPGAs are available) and have a real Linux distro running on an FPGA, rather slowly and with limited RAM. They even managed to make the ethernet port work using an entirely free stack (though you still unfortunately need Vivado for a while to compile it) and it's a step towards having an ASIC that is completely freely licensed. So it's still baby-steps but I'm glad the lowRISC project came back to life.

PinkMilkshake• 8 years ago

I've only had a passing interest in learning assembly. It's always been in the "maybe one day" category.

But after learning about how small the RISC-V instruction set is (less than 50 apparently, but I can't find a citation for that anywhere), I'm far more motivated to get into it.

krackers• 8 years ago

The base instruction set is small enough to fit on a card. Of course adding the floating point, vector extensions, etc. would make it a bit harder to squeeze into a single page, but I think it would still end up smaller than the x64 spec.

https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/...

trhway• 8 years ago

But after learning about how small the RISC-V instruction set is (less than 50 apparently, but I can't find a citation for that anywhere), I'm far more motivated to get into it.

from the times when x86 wasn't that big: http://pastraiser.com/cpu/i8080/i8080_opcodes.html

30 years ago we were typing the hex codes of those commands straight into the Forth words bodies using the mental copy of that table (as you see it has very logical easy to remember organization)

snvzz2• 8 years ago

Or the beautiful 68000.

http://goldencrystal.free.fr/M68kOpcodes-v2.3.pdf

IcePic• 8 years ago

Check out MSP430 is you want small instruction sets, also fits on one page if needed.

Posibyte• 8 years ago

I recommend the 6502[1] if you're just starting. What you learn applies almost everywhere, and it's very much a what-you-write-is-what-happens sort of processor. No branch prediction, no caches, no fancy features. Its op-set is very small and highly expressive. They still make them, in fact.

That said, whether you choose to start with it or RISC-V, from personal experience SiFive's implementations are phenomenal. I used one of their free-implementations, and I was blown away by how easy it was to use their automated tools to build a core exactly the way I wanted. Not as easy as generating a NIOS core, but much more capable. With an Artix-7, I had a very capable low-range processor in about an hour.

[1] https://skilldrick.github.io/easy6502/

masklinn• 8 years ago

If you just want to dip your hand in, chip8 is also a good starting point (if even less useful than 6502): where 6502 has about 80 actual opcodes acrosss ~50 mnemonics (https://en.wikipedia.org/wiki/MOS_Technology_6502#Assembly_l...) chip8 has 35 opcodes across 19 mnemonics (ADD, AND, CALL, CLS, DRW, JP, LD, OR, RET, RND, SE, SHL, SHR, SKNP, SKP, SNE, SUB, SUBN, XOR).

monocasa• 8 years ago

Having taught asm to people as their first language, I'd go with something like an MSP430. Since a 6502's registers are only half the pointer width, it really makes pointer manipulation more of a pain in the ass than it needs to be. That really obfuscates quite a.few.of the concepts that you're trying to learn by writing asm for a simple core.

pjc50• 8 years ago

I'm not sure that's a useful metric; in almost all architectures there's a "core" set which gets used the vast majority of the time in most programs, plus an increasing number of extensions for very specific purposes. You could start today on ARM with the top 20 instructions and get quite a long way.

pm215• 8 years ago

If you use a Cortex-M0 (v6M) then there are only 60 or so instructions total...

saagarjha• 8 years ago

MIPS isn't bad either. Both are pretty small and well-designed, and not particularly complicated.

protomyth• 8 years ago

The 6809 doesn’t get enough love. It was quite good for the era, easy to learn, and could support things like OS/9.

https://en.wikipedia.org/wiki/OS-9

mhb• 8 years ago

HiFive1 - Arduino RISC-V Dev Board

The HiFive1 is a low-cost, Arduino-compatible development board featuring the Freedom E310 making it the best way to start prototyping and developing your RISC‑V applications. Not only can the HiFive1 help build RISC-V platforms, but it is also the first commercially available option to do so! The HiFive1 can simply be plugged into your computer via the micro USB port located to the front of the board. Additionally, the HiFive1 comes programmed with a simple bootloader and a demo software, that way you aren’t restricted to the Arduino IDE if you don’t choose to do so.

https://www.sparkfun.com/products/15026

ivoras• 8 years ago

Hmm, does it really have only 16 KiB of RAM or am I misinterpreting the spec?

What would be the use case for a 320 MHz processor with 16 KiB RAM? Even ESP8266 has 80 KiB and runs at 80 MHz.

SloopJon• 8 years ago

The only place I see that mentions 16 KB is the instruction cache on the S7 monitor core. Apart from cache, it doesn't look like any of these include RAM.

crankylinuxuser• 8 years ago

That's fairly standard. The problem there is going to be attaching ddr3 modules to a board. BGA is a pain in the ass for anything past 10x10 using a toaster oven. And for doing it "right" you really need xray QA.

brianolson• 8 years ago

SiFive press release here: https://www.sifive.com/press/sifive-core-ip-7-series-creates...

aidenn03• 8 years ago

The M7 is an out-of-order processor, these all look to be in-order. Many artificial benchmarks (including Dhrystone) are very forgiving of in-order stages, so I would expect this to underperform relatively to a similarly benchmarked M7.

Zeetah• 8 years ago

M7 is actually an in-order processor. It does have six-stage dual-issue pipeline.

aidenn03• 8 years ago

Oh you're right. It has speculative execution, but is otherwise strictly in-order, my mistake.

microcolonel• 8 years ago

Apparently good Cortex-M7s get around 5 CoreMark/MHz (NXP crossover, STM32H7), so it's almost identical per MHz, and I'm willing to bet that they can get higher frequencies with less effort (if you look at the SiFive MCUs, they run at stupid frequencies compared to similar competing cores, and were generally available almost two years ago now). For further comparison, the Broadwell Xeon I'm typing this on gets about 7.2 CoreMark/MHz (running at full turbo, 4GHz, on one core).

jabl• 8 years ago

Is this based on the open source rocket chip, or is it a proprietary design?

SiFive Introduces 7 Series RISC-V Cores with E7, S7 and the U7 Series

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