inkyoto

[…] why the building does not have high quality NBN connections?

Because their place of residence is connected to an embedded network that has eschewed the NBN Co and chosen to connect to a private fibre operator who sits outside the NBN. They probably also pay more compared to NBN for the same speed.

Not every embedded network supplies fibre, but some do, and that appears to be the case in their situation.

By the way, NBN has recently upgraded the network to 2Gbps, with 10 Gbps having been trialled but no availability date set as of yet.

«Mates rates» is a big problem in Australia, indeed. At best, it is collusion, but typically it is corruption.

I have recently gone through the entire chain of complaints, the ombudsman including, and I have gained plenty of insight into how insidious the current scheme is.

NSW has set out to do something about it, with price caps being introduced in 2027. If you live in NSW, make your submission to the regulator (IPART) ASAP – submissions are closing at the end of July.

No, technically it can't. An individual writing to an MP is rarely sufficient by itself.

Australia’s embedded network landscape is a peculiarly intricate tangle of nuance, complexity and regulatory optimism. Note that the embedded networks are distinctly unique and different from retail utility providers.

Please bear with my lengthy explanation for a few rather long moments.

Embedded networks are private distribution systems sitting behind a single connection to the public grid (shopping malls, apartment blocks, retirement villages, camp and caravan sites etc). They all have, effectively, a single wire going into the site.

Originally, they were designed for incidental on-selling by site managers, and they are a regulatory exception allowing the operator to on-sell electricity and other services without becoming a fully authorised energy retailer or licenced distributor. The embedded networks typically bundle: 1) electricity, 2) centralised hot water, 3) cold water, 4) gas, 5) heating / cooling (air-conditioning) and 6) fibre to the premises (sometimes, not always). All those things are governed by separate statutes.

In theory as well as occasionally in practice, they should be cheaper for consumers because they are able to negotiate lower wholesale rates from the upstream supplier and because the customer churn is non-existent (the customer is locked into the network and has nowhere to go). In some cases, that is indeed true, but because the current legislation explicitly excludes the embedded networks from the government reporting, many embedded network operators have resorted to the insidious exploitation of their customers, and the government is clueless because the operators' imposed pricing is opaque.

Natiaonally, Australia does not have a single federal embedded-network statute. The principal framework is a cooperative national scheme comprising 7 government bodies (Australian Energy Market Commission, AER, Australian Energy Market Operator, National Electricity Law and Rules, National Energy Retail Law and Rules, Australian Consumer Law and Australian Competition and Consumer Commission).

At the state level – so far – only Victoria has largely banned new embedded networks, with the remaining states either participating or not participating in the National Energy Customer Framework. Overall, NSW, Victoria, Western Australia and the national regulators are tightening the rules but they still have a way to go.

For a reform such as embedded-network regulation, the path looks closer to:

  Voters ↝ political parties ↝ MP's ↝ ministers ↝ departments ↝ intergovernmental bodies ↝ regulators ↝ consultation processes ↝ rule-making bodies ↝ implementation.

Unsurprisingly and consequently, politicians become heavily dependent on: a) departmental advice, b) regulator advice, c) industry submissions, d) consultant reports, and e) lobby groups.

The people who understand the system – and especially those one who know how to work the system to their benefit – therefore acquire disproportionate influence over how the system evolves. That does not necessarily imply corruption, it is a structural feature of technical governance. Customers, however, refer to it as «rent seeking», even if they own an apartment.

Despite all that, elected representatives still do remain one of the few machineries capable of changing the underlying legal framework. The deeper issue is that modern regulatory states are neither pure democracies nor pure technocracies – they are hybrids. Formal authority remains democratic, but practical power is distributed among elected officials, bureaucracies, regulators, courts, industry participants, consultants, lobbyists and organised interest groups.

I have recently gone down the rabbit hole of the embedded networks and learned a bewildering number of things hence the fulmination.

Performance gap is not closing in specimens commercially available today, and the promises of it «happening any moment from now» are now indistinguishable from monthly horoscopes.

For example, Zen 2 is a 2019 design, and the 64-core SG2044 C920v2, which was released in May 2025, a three-decode, four-dispatch core at about 2.6 GHz, with 128-bit vectors is still approximately[0]:

  – 9 times slower in the block tridiagonal solver at 64 cores;

  – 2.05 times slower in the lower-upper Gauss-Seidel solver;

  – 2.05 times slower in the scalar pentadiagonal solver.

The reason why those three solvers are particularly interesting, especially in the HPC scenario, is because all three exercise substantial amounts of (unlike hobbyist and similar synthetic benchmarks):

  – Floating-point computation;

  – Memory hierarchy behaviour;

  – Cache utilisation;

  – Synchronisation;

  – Compiler optimisation;

  – Overall processor throughput.

[0] https://arxiv.org/html/2508.13840v1

[1] https://arxiv.org/abs/2508.13840v1

[…] they are legally allowed to sign binding contracts with the building manager […]

The embedded networks collude with the builders and offer them the installation of wiring, air-conditioning, gas, hot water, and sometimes the internet – usually for free – and that happens before the strata comes into the picture. The strata is left with no choice but to inherit a fixed-term contract (typically 3-5 years), after which it can switch to… another embedded network.

The builders accept offers from embedded networks because it reduces their overall costs.

The NSW government has enacted the first tranche of regulations for embedded networks from the 1st of July this year, with the embedded networks price caps being introduced in early 2027 (that is the promise, anyway). If you live in NSW, IPART is the government body in charge of the regulation, and it is accepting submissions until the end of this month. Prepare and make your own submission whilst you can, as I have done.

Moreover, apartment dwelling residential customers connected to embedded networks (many new apartment blocks in NSW, Victoria and Queensland) are not eligible for the Solar Share Offer because under section 6(3)(c), a consumer supplied through an embedded network is already excluded from the Commonwealth Electricity Retail Code’s definition of a «small customer».

The government won't address this particular perverse situation with the embedded networks until the 2027–28 DMO period.

There are not.

x86 is an ancient design mired in legacy and problems, so Intel/AMD Intel and AMD had to make it work for a modern world even if that involved kludges, band-aids, and crutches. Whilst you do have a point there, personally I do not find x86 particularly interesting to discuss.

I did not have Qualcomm and their latest bout of theatrical shenanigans concerning C in mind, either.

Back onto C.

  – C demonstrably improves code density;

  – Improved code density is conducive of better instruction cache utilisation and reducing the pressure on the TLB;

  – Mixed-width decoding (a trade-off) demonstrably adds front-end work (especially in pathological cases[0]);

  – No publicly benchmarked RISC-V processor is sufficiently contemporary and wide (or very wide) to impart the net effect of that trade-off at the highest performance tier;

  – Performance targets (aarch64 and x86-64) are moving faster than publicly demonstrated performance of existing RISC-V implementations in silicon, and the gap is not closing in.

[0] The second page is not resident, the decoder can't proceed because the second half-word can't be obtained, the access generates a page fault, the CPU eventually vectors to the page-fault handler. Genuine page faults are extremely expensive.

[…] and hold on to 2 bytes from the previous cache line if there was 1/2 a 32-bit instruction at the end of the previous cache line […]

Well, and that is the worst case scenario from the performance standpoint since, if a 32-bit instruction is spans a page boundary, it will result in a page fault stalling the instruction decoder.

It might be acceptable in implementations not sensitive to such an overhead (e.g. embedded solutions) but is wholly unacceptable in high performance scenarios.

Sun was one of the few RISC design houses who stubbornly resisted NUMA in favour of SMP, which they have perfected in the hardware and in the software (Solaris). The «Solaris internals» book discusses the subject of SMP vs NUMA vs ccNUMA in the «Parallel systems architectures» section (3.2).

You might be thinking SGI who went in big on NUMA. IBM and HP have also built ccNUMA systems (e.g. HP Superdome and Superdome 2).

Well. The Latin version of Roman is Romanus, which is believed to have descended from Romulus, one of the two legendary founders of Rome.

The popularity of Roman in Eastern and Western Slavic cultures is likely due to the cultural influence of the Byzantine Empire. Roman is also a rather popular name in Spanish speaking Latin American countries (Román) and is not entirely unknown in Germany (same spelling).

It is exactly the other way round: JSON-LD has largely displaced and superseded RDF/XML in many web applications.

kowtow (叩頭) is a Cantonese word borrowed into English in the early 19th century.

I see Swift as a more approachable version of Rust.

If somebody is mulling over Rust but finds it too difficult to grasp, they could start off with Swift first and then move over to Rust.

One of the main advantages of Rust is a more developed and thriving ecosystem.

Not just interoperability with Objective C but with C (full) and C++ (increasingly better but not full) as well.

Swift is also interoperable with different versions of itself courtesy of the Swift stable ABI (Application Binary Interface)[0], which they invested a significant amount of time into at the expense of adding other new features to the language, which have come along later.

Rust offers a different approach: recompile everything and static linking.

[0] https://faultlore.com/blah/swift-abi/

I got my first bifocals last year. I got the "no line" variety and, so far, I hate them.

They are called progressives (or multi-focal – depending on whom you speak with).

Progressives come in a few «ranges»: near-range, mid-range and all-purpose. There are also «premium» options available, although I am not entirely sure how much different they actually are.

I have found that having two separate pairs of progressives (near-range for reading, laptop use and all-purpose for everything else) works the best. All of them can also be had as the transition variety and with different tint colours, thus obviating the need for a separate pair of shades.

In fact, when I first tried the near-range progressives some 5 years ago, it was an eye-opener in the almost literal sense of the word – the laptop screen flattened and became bigger despite obviously not changing its physical size. It was something that I had struggled with for a long time before the progressives entered mainstream. At high prescription numbers, the lenses for myopia start distorting the true shape of objects which creates mild to substantial visual discomfort, and near-range progressives fix that.

Another source of discomfort might be the suboptimal «Add» number on the script for progressives. This can be fixed by going to an optometrist clinic rather that a street optometrist (or find a reputable and good one first). If the «Add» is too small, the progressives will make little difference compared to conventional lenses, and, if it is too big, they will make it difficult to see in the distance.

Based on own subjective experience, I can't recommend the progressives enough, although a little bit of fine-tuning might be required (none in my case).

The vast majority of virtual machines, including JVM and .NET, are stack based.

And, whilst compiling C and C++ the JVM / .NET CLR byte codes is very uncommon, both VM's have become very popular compilation targets for other programming languages.

Rotating register windows are a distinguishing feature of the Berkeley RISC design, which predates VLIW by at least a decade.

"PLEASE COME FROM" is one of the eldritch horrors of software development.

The most enigmatic control flow statements in INTERCAL, however, remain PLEASE GIVE UP and DO ABSTAIN FROM – a most exalted celebration of pure logic and immaculate reason.

Once again – respectfully – this remains largely twaddle as the facts themselves state otherwise.

Even at the microarchitecture level, the hard part is not raw CISC-ness but irregularity and compatibility baggage. In that respect x86 was usually the uglier customer.

High-end x86 implementations ultimately scaled further because Motorola had less market pressure and fewer resources than Intel to keep throwing silicon at the problem, not because m68k was somehow harder to optimise.

Later high-performance m68k cores did what later x86 cores also did: translate the architected variable-length instruction stream into a more regular internal form. Motorola’s own MC68060 manual says the variable-length M68000 instruction stream is internally decoded into a fixed-length representation and then dispatched to dual pipelined RISC execution engines. That is not evidence of an ISA that was uniquely resistant to microarchitectural optimisation. It is evidence that Motorola used the same broad trick that became standard elsewhere: hide ISA ugliness behind a cleaner internal machine.

There is also a deeper point. The m68k ISA was rich, but it was comparatively regular and systematic at the architectural level. The m68k manuals show a clean register model and – notably – consistent condition-code behaviour across instruction forms. That kind of regularity is exactly what tends to help both compiler backends and hardware decode/control design. By contrast, x86’s biggest hardware pain historically came not from being «less CISC» than m68k, but from being more irregular and more burdened by backward compatibility.

Lastly, but not least importantly, CPU's were not the core business of Motorola – it was a large communications-and-semiconductors company, with the CPU's being just one product family within a much larger semiconductor business.

There was no clear understanding within the company of the rising importance of CPU's (and computing in general), hence the chronic underinvestment in the CPU product line – m68k did not see the light of highly advanced, performant designs purely because of that.

Respectfully, this is nonsense.

«More CISC-y» does not by itself mean «harder to optimise for». For compilers, what matters far more is how regular the ISA is: how uniform the register file is, how consistent the condition codes are, how predictable the addressing modes are, and how many nasty special cases the backend has to tiptoe around.

The m68k family was certainly CISC, but it was also notably regular and fairly orthogonal (the legacy of the PDP-11 ISA, which was a major influence on m68k). Motorola’s own programming model gives one 16 programmer-visible 32-bit registers, with data and address registers used systematically, and consistent condition-code behaviour across instructions.

Contrast that with old x86, which was full of irregularities and quirks that compilers hate: segmented addressing, fewer truly general registers (5 general purpose registers), multiple implicit operands, and addressing rules tied to specific registers and modes. Even modern GCC documentation still has to mention x86 cases where a specific register role reduces register-allocation freedom, which is exactly the sort of target quirk that makes optimisation more awkward.

So…

  68k: complex, but tidy

  x86: complex, and grubby

Since when were payment networks latency sensitive?

Since the advent of e-commerce, POS-networking and fraud detection systems in 1990's-2000's.

User-facing and authorisation path are highly latency sensitive. It includes tap-to-pay, online checkout, issuer authorisation, fraud decisioning, and instant payment confirmation – even moreso for EFT payments.

[…] 2-5 seconds more from card presentation to getting approval back.

This is the mid-1990's level QoS when smaller merchants connected the acquirer bank via a modem connection, and larger ones via ISDN.

Today, payments are nearly instant in most cases, with longer than one-second card payment flows falling into the exceptions territory or inadequate condition of the payment infrastructure.

As well as to eggplant and belladonna.

PDP-11 was a major source of inspiration for m68k architecture designers. The influence can be seen in multiple places, starting from the orthogonal ISA design down to instruction mnemonics.

It is quite likely that not allowing the misaligned access was also influenced by PDP-11.

PDP-11, m68k – to name a few, did not allow misaligned access to anything that was not a byte.

Neither are RISC nor modern.

If I'm not mistaken, microcode is a thing at least on Intel CPU's, and that is how they patched Spectre, Meltdown and other vulnerabilities – Intel released a microcode update that BIOS applies at the cold start and hot patches the CPU.

Maybe other CPU's have it as well, though I do not have enough information on that.

In Linux the default swap behaviour is to also swap out the memory mapped to the executable file, not just memory allocated by the process […] I believe both Windows and macOS don't swap out code pages, so the applications remain responsive, at the of (potentially) lower swap efficiency

Linux does not page out code pages into the swap. You might be conflating page reclamation with swapping instead.

In Linux, executable «.text» pages are mapped[0] as file-backed pages, not anonymous memory, so when the kernel needs to reclaim RAM it normally drops those pages and reloads them from the executable file on the next page fault once they are accessed again (i.e. on demand) rather than writing them to swap.

In this particular regard, Linux is no different from any other modern UNIX[1] kernel (*BSD, Solaris, AIX and may others).

[0] Via mmap(2) in argv[0], essentially.

[1] Modern UNIX is mid-1990's and onwards.

In 1970 it might have been the only way to provide a flexible API, but nowadays we have a great variety of extensible serialization formats better than "struct".

Actually, fork(2) was very inefficient in the 1970's and for another decade, but that changed with BSD 4.3 which shipped an entirely new VMM in 1990 in 4.3-Reno BSD, which – subsequently – allowed a CoW fork(2) to come into existence in 4.4 BSD in 1993.

Two changes sped fork (2) up dramatically, but before then it entailed copying not just process' structs but also the entire memory space upon a fork.

What are we comparing Ada to… PHP?

I do not need to search the internet as I am fluent at German as well.

The knowledge of Modern High German helps little to none as far as the comprehension of Old English is concerned. From a modern German speaker's perspective, Old English – with a relatively small number of exceptions – is gibberish.