Book: RISC-V System-on-Chip Design

Judging by the authors, I'm sure the book will be excellent. Hopefully it will be available through O'Reilly Online, because the price is a bit steep.

tolerance• 11 days ago

You know what. I feel like it’s a fair price.

sylware7• 11 days ago

Everything RISC-V is good (even the mistakes which is making it more robust and more mature).

timhh4• 11 days ago

I like RISC-V (it's been my job for the last 7 years) but this is nonsense. Not everything RISC-V is good. CLIC was awful (thankfully it has been abandoned). The spec is not especially well written - the style is inconsistent due to being written by many authors, and it is waaaay too much of a textbook rather than a proper spec. (There is some ongoing work to improve this tbf.)

There's a practically unending list of undefined/implementation defined behaviours, which is great if you want to implement an ultra minimal microcontroller with 100 flops, but pretty awful otherwise.

Requiring the C (compressed) extension in the RVA profiles was definitely a mistake. The lack of true 16/64kB pages and conditional moves are probably a mistake (though fixable).

I don't know how any of these make it more robust and mature.

(But to be clear, I still think it's pretty good overall.)

rwmj7• 11 days ago

I broadly agree with your points except one.

Requiring C (compressed) is necessary to avoid splitting the Linux ecosystem. Chips lacking C would never be able to run binaries compiled with C. There's no practical way for such binaries to detect this and work around it at runtime as they can with other extensions. And emulation would be super-slow given a large proportion of instructions are compressed.

Also the excuse given by Qualcomm - that it would make all instructions fixed length and so much easier to decode - is just wrong. RISC-V supports variable length instructions, even much longer than 32 bits, and you've just got to deal with it. Just because Qualcomm acquired a company with a microarchitecture that could only deal with fixed length instructions is no reason to break the ecosystem.

Also interested in the problems you see in Zicond. It claims at least to give you most of the benefit of conditional moves using only two instructions, but I've not actually tried using it. (https://docs.riscv.org/reference/isa/extensions/zicond/_atta...)

sylware7• 11 days ago

English is not my native language and I wrote a bit too fast the message: I wanted to say that "everything pushing forward RISC-V is good".

I code RISC-V assembly, I don't use C machine instructions (I don't even use the pseudo-instructions, ABI register names and dodge nearly all ISA extensions, I try to stick to core as much as I can). I run my code on x86_64 linux with a small interpreter written in x86_64 assembly (thx to the 'R' in RISC).

I wonder if there are some 'broad and not niche, real-life' speed benchmark numbers to show how much C machine instructions are worth.

For the moment, I see those C machine instructions more as a marketing extension to match their arm equivalent: you know, for those key deciding people who care more about the amount of features and not their contextual pertinent usage.

To say an ISA is "good" is related to some set of technical sweet spots based on compromises based on projected usages.

RVA from my point of view is mostly preparing RISC-V hardware for some level of x86_64/arm compatibility.

I wonder if there are RISC-V implementations using the latest silicon process from TSMC.

flopsamjetsam2• 11 days ago

CLIC was awful (thankfully it has been abandoned)

Could you expand a little on what made it a bad design? I'm not much up on RISC-V.

chris_money202• 11 days ago

Based on description it doesn't sound like SoC design, it sounds like a book about RISC-V microprocessors. To the untrained eye, that sounds similar, but a microprocessor is one part of an SoC, and sometimes it can be a very small part based off the role the microprocessor plays.

henrymerrilees• 11 days ago

Disclaimer up front: I've only read ~10/23 RVSoC draft chapters that were made available as a part of SP2025 E154, so don't take me as any kind of authority on the remaining 13, which I can't wait to get my hands on!

In the preface on xx-xxi:

```

This book took three years of development and another year of production. There are many more important topics in computer architecture and SoC design that were omitted from this edition for schedule reasons; we hope to address them in a future volume:

* Multicore

  * Multilevel cache coherency
  * Synchronization
  * Interprocessor communication

* Microarchitecture

  * Superscalar
  * Out-of-order
  * Deeper pipelines

* RISC-V Extensions

  * Vector
  * Hypervisor
  * Debug
  * Trace

* Verification

  * Functional coverage metrics
  * Hardware emulation

* SoC Design

  * Intellectual property block design and integration
  * AXI interfaces
  * Accelerators
  * Memory controllers
  * Network-on-chip

* SoC Implementation

  * Timing and power optimization
  * Clock gating
  * Clock domain crossings
  * External interfaces

```

It's definitely processor-centric but I wouldn't say "about RISC-V microprocessors" catches it either. The book is certainly structured around the core, but arguably so too is SoC design, at least at an introductory level. RVSoC uses a real SoC design (CORE-V Wally), and each aspect is covered at a length more or less proportionate to the complexity of its implementation in Wally. Admittedly, Wally's peripherals are fewer and simpler than you might find out in the wild. Wally itself is 80-90% core by lines of RTL (horrible complexity metric I know, sorry).

Another way to look at the book is that it picks up where Digital Design and Computer Architecture (by the same Harris and Harris) leaves off. DDCA is used to teach the E85 course at Harvey Mudd; RVSoC is used to teach E154 (SoC design). DDCA builds up to a simplified RV32I-subset pipelined core. If RVSoC started with peripherals without fully elaborating the core, it would leave both readers of both books and students of both courses with a gap in coverage on core design compared to the depth of the remainder of both books.

Both are very detailed. With RVSoC at 859 pages in print and 1135 after the digital supplement, the core-related chapters are not by any means stealing airtime from the other components of the SoC, you could strip out every core-related page and still have a modestly-sized textbook. While not by any means an encyclopedic reference for SoC design, I found it to be a wonderful bridge from more elaborated microarchitecture into SoC.

I hope they are able to get that future volume out!

(edit: quote formatting)

imtringued• 10 days ago

Uh, I don't know what's still in there. Based on your exclusion list you've dropped all the core SoC topics...

Like how do you even build a SoC if you don't talk about how to build the peripherals or how to wire them up?

genxy• 11 days ago

Excellent find, an academic paper announcing the book is here

https://peer.asee.org/57147.pdf

Harris and Harris (no relation) have an excellent book on digital design using RISC-V as the domain problem, https://pages.hmc.edu/harris/ddca/ddcarv.html

https://pages.hmc.edu/harris/ddca/

Their books are perfect, and I hope this textbook gets adopted by thousands of colleges. Our RISC-V future is bright, now we need one on SoC bringup and getting your OS running on that SoC.

homarp• 11 days ago

and the associated github https://github.com/openhwgroup/cvw

flopsamjetsam2• 11 days ago

I re-took Computer Architecture recently, and we used their earlier book "Digital Design and Computer Architecture: ARM edition", and it was also excellent.

whateverboat• 10 days ago

Why do you say (no relation) when the authors are exactly the same?

gertrunde• 10 days ago

Not sure about "David Harris" and "Sarah L. Harris" being exactly the same...?

Jtsummers2• 10 days ago

They mean between the authors. It's a common added expression when discussing two or more people whose names suggest a familial relationship but there isn't one.

rramadass2• 11 days ago

What are some good books/resources on overall System-On-Chip Design?

There is a surprising paucity of material on SoC design which are comprehensive and complete. Application-specific tailored features, Cost, Performance, Area, Power etc. all go into SoC design and yet there does not seem to be a comprehensive resource bringing everything together. Even wikipedia isn't detailed enough - https://en.wikipedia.org/wiki/System_on_a_chip

I know of only two decent books viz. Computer System Design: System-on-Chip by Michael Flynn and Wayne Luk (this is pretty good) and the older ARM System-on-Chip Architecture by Steve Furber.

oumua_don17• 11 days ago

There's also Modern System-on-Chip Design on Arm textbook by David J. Greaves and it's available as a free download [1].

[1] https://www.arm.com/resources/education/books/modern-soc

rramadass2• 11 days ago

Nice; thanks for the pointer.

Searched Amazon for other books on SoC design and found a series of books by Dr. Veena S. Chakravarthi which seem quite comprehensive - https://www.amazon.com/s?k=Veena+S.+Chakravarthi&i=stripbook...

spzb• 11 days ago

A couple of sample chapters are available here https://pages.hmc.edu/harris/ddca/rvsocd.html

xqb64• 11 days ago

Andy Tanenbaum style cover.

Book: RISC-V System-on-Chip Design

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