Evaluating the Infinity Cache in AMD Strix Halo

https://chipsandcheese.com/p/evaluating-the-infinity-cache-in

by zdw • 9 months ago

147 67 9 months ago

Despite this APU being deeply interesting to people who want to do local AI, anecdotally I hear that it’s hard to get models to run on it.

Why would AMD not have focused everything it possibly has on demonstrating and documenting and fixing and showing and smoothing the path for AI on their systems?

Why does AMD come across as so generally clueless when it comes to giving developers what they want, compared to Nvidia?

AMD should do whatever it takes to avoid these sort of situations:

https://youtu.be/cF4fx4T3Voc?si=wVmYmWVIya4DQ8Ut

typpilol2• 9 months ago

Any idea what makes models hard to run on it?

Just general compatibility between Nvidia and AMD for stuff that was built for Nvidia originally?

Or do you mean something else?

cakealert• 9 months ago

It's not the models, it's the tooling. Models are just weights and an architecture spec. The tooling is how to load and execute the model on hardware.

Some UX-oriented tooling has sort of solved this problem and will run on AMD: LM Studio

pella• 9 months ago

"The AMD Ryzen™ AI Max+ processor is the first (and only) Windows AI PC processor capable of running large language models up to 235 Billion parameters in size. This includes support for popular models such as: Open AI's GPT-OSS 120B and Z.ai Org's GLM 4.5 Air. The large unified memory pool also allows models (up to 128 Billion parameters) to run at their maximum context length (which is a memory intensive feature) - enabling and empowering use cases involving tool-calling, MCP and agentic workflows - all available today. "

  GPT-OSS 120B MXFP4              : up to 44 tk/s
  GPT-OSS 20B MXFP4               : up to 62 tk/s
  Qwen3 235B A22B Thinking Q3 K L : up to 14 tk/s
  Qwen3 Coder 30B A3B Q4 K M      : up to 66 tk/s
  GLM 4.5 Air Q4 K M              : up to 16 tk/s

(performance tk/s ) : https://www.amd.com/en/blogs/2025/amd-ryzen-ai-max-personal-...

andrewstuart2• 9 months ago

I’m not sure why you are telling me this.

storus• 9 months ago

Strix Halo can only allocate 96GB RAM to the GPU. So GPT-OSS 120B can be ran only at Q6 at best (but activations would need to be partially stored in the CPU mem then).

yencabulator2• 9 months ago

Qwen3 Coder 30B A3B Q4 K M : up to 66 tk/s

For comparison, a Ryzen 9 8945HS runs that around 21 tokens/sec on pure CPU at price point around $479 (RAM not included), where newer computers with this chip are >$2000 (RAM soldered on).

lmm• 9 months ago

Hardware companies are extremely bad at valuing software. The mystery isn't that AMD is bad at it, the mystery is that NVidia is good at it. They also have a probably 30-40 year head start. AMD is trying as much as they can, but changing culture takes time.

DeepYogurt• 9 months ago

Intel and arm are also pretty good at it. amd feels like the outlier here

ur-whale• 9 months ago

the mystery is that NVidia is good at it

They are absolutely not.

Just less bad than AMD, which is an extremely low bar.

naasking• 9 months ago

They also have a probably 30-40 year head start.

Holy exaggeration Batman!

sidkshatriya• 9 months ago

Why does AMD come across as so generally clueless when it comes to giving developers what they want, compared to Nvidia?

I have some theories. Firstly, Nvidia was smart enough to have a unified compute GPU architecture across all its architectures -- consumer and commercial. AMD has this awkward split between CDNA and RDNA. So while AMD is scrambling to get CDNA competitive, RDNA is not getting as much attention as it should. I'm pretty sure its ROCm stack has all kinds of hacks trying to get things working across consumer Radeon devices (which internally are probably not well suited/tuned for compute anyways). AMD is hamstrung by its consumer hardware for now in the AI space.

Secondly, AMD is trying to be "compatible" to Nvidia (via HIP). Sadly this is the same thing that AMD did with Intel in the past. Being compatible is really a bad idea when the market leader (Nvidia) is not interested in standardising and actively pursues optimisations and extensions. AMD will always play catch up.

TL;DR AMD made some bad bets on what the hardware would look like in the future and never thought software was critical like nvidia.

AMD now realizes that software is critical and what future hardware should look like. However it is difficult to catch up with Nvidia, the most valuable company in the world with almost limitless resources to invest in further improving its hardware and software. Even while AMD improves, it will continue to look bad in comparison to Nvidia as state of art keeps getting pushed forward.

positron262• 9 months ago

While Nvidia's strategic foresight explains why Nvidia is ahead, it doesn't quite capture why the challenge is not something that only AMD can or should tackle alone.

The 7,484+ companies who stand to benefit do not have a good way to split the bill and dogpile a problem that is nearly impossible to progress on without lots of partners adding their perspective via a breadth of use cases. This is why I'm building https://prizeforge.com.

Nvidia didn't do it alone. Industry should not expect or wait on AMD to do it alone. Waiting just means lighting money on fire right now. In return for support, industry can demand more open technology be used across AMD's stack, making overall competition better in response for making AMD competitive.

z3ratul1630712• 9 months ago

we can blame individual bad decisions, but imo it all stems from the culture of viewing software as a cost center and messing it up from there.

alessandru2• 9 months ago

radeon historically gimped the double precision less badly than nvidia, one might say radeons were more suited for scientific compute. actual scientific compute that cares about numbers and precision.

idk about bad bets, they were just slow to release rdna for desktop when they had it already for consoles. there wasn't conflict between cdna and rdna, cdna was product for their data center. they slow-walked rdna chips because they were busy selling them to consoles. and they never invested in software like nvidia did. they wanted outside people to make openCL work when nvidia was directly investing.

these kind of amateur takes are like a poor distillation of whatever you read in the hardware news. sorda muddying the waters a bit with your confusion.

FuriouslyAdrift3• 9 months ago

AMD announced they are unifying their GPU compute (Instinct) and GPU (RDNA) architectures in the next generation.

JonChesterfield3• 9 months ago

One issue is you need rocm 7 which only just came out.

Another is that people unsportingly write things in cuda.

It'll be a "just works" thing eventually, even if you need software from outside AMD to get it running well.

rbanffy2• 9 months ago

Another is that people unsportingly write things in cuda.

Whether we like it or not, CUDA is the de-facto standard for these things. I wonder how much effort would it take for a company the size of AMD to dedicate a couple million dollars a year to track CUDA as closely as feasible. A couple million dollars is a rounding error for a leading silicon maker.

aaryamanv• 9 months ago

You can run ROCm and PyTorch natively for strix halo on both windows and linux. See https://rocm.docs.amd.com/en/docs-7.9.0/index.html

dontlaugh• 9 months ago

It’s a gaming chip.

green7ea2• 9 months ago

I have a Strix Halo based HP ZBook G1A and it's been pretty easy getting local models to run on it. Training small LLMs on it has been a bit harder but doable as well. Mind you, I 'only' have 64 GB with mine.

Under Linux, getting LM Studio to work using the Vulkan backend was trivial. Llama.cpp was a bit more involved. ROCm worked surprisingly well with Arch — I would credit the package maintainers. The only hard part was sorting out Python packaging for PyTorch (use local packages with system's ROCm).

I wouldn't say it's perfect but it's definitely not as bad as it used to be. I think the biggest downside is the difference in environment when you use this as a dev machine and then run the models on NVIDIA hardware for prod.

ctas• 9 months ago

Can you share a bit more on the small LLMs you've trained? I'm interested in the applicability of current consumer hardware for local training and finetuning.

drcongo• 9 months ago

I don't know why you're getting downvotes on this, my experience matches it. I have an Evo-X2 which has Strix Halo and rocm still doesn't officially support it. "Support" is supposedly coming in 7.0.2 which can be installed as a preview at the moment but people are still getting regular and random GPU Hang errors with it. I'm running Arch and I've had to make a bunch of tasks in a mise.toml so that I don't forget the long list environment variables to override various rocm settings, and even longer list of arcane incantations required to update rocm and PyTorch to versions that actually almost work with each other.

fluoridation2• 9 months ago

AMD should do whatever it takes to avoid these sort of situations:

LOL. How is it AMD's fault that the AI application ecosystem is a clusterfuck?

epistasis• 9 months ago

Great article on performance. This video from a few weeks ago goes into chiplet design a bit more too:

https://youtu.be/maH6KZ0YkXU

joelthelion2• 9 months ago

I don't quite get it. What's so special about having 32MB of cache? Why is it called "infinity"?

noelwelsh• 9 months ago

This article from the same site goes into the Infinity Cache design in a bit more detail: https://chipsandcheese.com/p/amds-cdna-3-compute-architectur...

The summary is that it's a cache attached to the memory controllers, rather than the CPUs, so it doesn't have to worry about cache coherency so much. This could be useful for shared memory parallelism.

joelthelion2• 9 months ago

Thank you!

jbreitbart• 9 months ago

Since it is attached to the memory controller, one could argue that it is truly the final level of the cache hierarchy and the term infinity is not only a marketing term.

p_l• 9 months ago

IBM Power8 and Power9 used Centaur chips which had similar "last level cache" onboard.

Because it is last level before the actual ram chips, no coherency involved.

MisterTea• 9 months ago

Sounds a bit like a tightly coupled memory (TCM) in an embedded CPU; Fast single cycle RAM shared across the system.

pixelpoet• 9 months ago

What makes Intel's SMT implementation "hyper"? What makes Mario "Super"? It's just marketing.

themafia• 9 months ago

What makes Mario "Super"?

The Super Mushroom power-up.

arjvik• 9 months ago

Hyperthreading is technically a level above superscalar?

dripdry45• 9 months ago

Apparently, Mario actually was the super for the building that they were in. He was not super, he was the super (supervisor) fixing stuff

phire• 9 months ago

AMD named their memory fabric "infinity fabric" for marketing reasons. So when they developed their memory attached cache solution (which lives in the memory fabric, unlike a traditional cache), the obvious marketing name is "infinity cache"

The main advantage of a memory attached cache is that it's cheaper than a regular cache, and can even be put on a seperate die, allowing you to have much more of it.

AMDs previous memory fabric from the early 2000s was called "Hyper Transport", which has a confusing overlap with Intel's Hyper Threading, but I think AMD actually bet intel to the name by a few years.

typpilol2• 9 months ago

How's latency vs a traditional?

FuriouslyAdrift3• 9 months ago

Infinity Fabric is, in fact, the current superset of HyperTransport. HyperTransport is an IO architecture for chip to chip communication and has been used by pretty much everyone. It's also an open spec and has a consortium managing it.

https://en.wikipedia.org/wiki/HyperTransport

adrianmonk• 9 months ago

Confusing, yes, but at least they didn't call it "HyperLink".

Also, Ross Technology beat them both to "hyper" names with the hyperSPARC CPU.

Evaluating the Infinity Cache in AMD Strix Halo

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