ARM Goes 64-bit

http://www.realworldtech.com/arm64

by enos_feedler • 14 years ago

123 60 14 years ago

ajross2• 14 years ago

It's interesting to see a very x86_64-like attempt to shake off the weirdness of the ancestral architecture here. The PC is no longer an addressable register. Thumb has been dropped. The predication bits are no more. The weird register aliasing thing done by NEON is gone too. The register banking (and it seems most of the interrupt architecture) is entirely different.

And, just like in the Intel world, market pressures have introduced all new CISC quirks: AES and SHA256 instructions, for example.

But of course an architecture document does not a circuit make. All the weirdness (old and new) needs to be supported for compatibility (OK, maybe they can drop Jazelle), so the fact that they no longer talk about some things doesn't really save them any transistors in practice.

Honestly, this is sounding more like an Intel or AMD part, not less.

enos_feedler3• 14 years ago

Yes, its too bad cleaning up the architecture doesn't necessarily cleanup the physical design. As GPUs have been more recent entrants to the general purpose space it is clear they are trying to avoid the same mistakes. The only place you will find a a true GPU binary is buried deep in the memory of the runtime stack (for NVIDIA at least, not sure about AMD).

ajross2• 14 years ago

Right. My understanding is that NVIDIA has mucked around with their low level instructions at every iteration. I remember reading somewhere that with Kepler the hardware doesn't even have dependency interlocks -- the compiler is responsible for scheduling instructions such that they don't use results that aren't ready yet.

But at the same time the lack of a clear specification and backwards compatibility means that the software stack needs to deal with all new bugs (both hardware and software) at every iteration. That puts a IMHO pretty firm cap on the "asymptotic quality" of the stack -- you're constantly chasing bugs until the new version comes out. So you'll never see a GPU toolchain of the quality we expect from gcc (or LLVM, though that isn't quite as mature).

pjscott• 14 years ago

Is having hardware acceleration for AES and SHA256 really a "CISC quirk", or just a really specialized set of arithmetic instructions? The classic RISC idea of making the core simple and fast doesn't really apply here; internally, it's all simple micro-operations driving special-purpose hardware. It seems similar to having a fused multiply-accumulate operation: they've figured out how to accelerate the core of a common task, and this is the API they've decided to give it.

enos_feedler3• 14 years ago

most likely for energy-efficiency reasons.

simcop2387• 14 years ago

That's actually an almost reasonable definition of CISC for laypeople. Take a look at the definition on wikipedia.

  A complex instruction set computer (CISC, play /ˈsɪsk/)
  is a computer where single instructions can execute several 
  low-level operations (such as a load from memory, an arithmetic 
  operation, and a memory store) and/or are capable of multi-step
  operations or addressing modes within single instructions.

Now the reality is that on the whole things are not quite as cut and dry. In this case they're doing it to give access to dedicated hardware for power gains most likely, which is why something that's typically close to RISC would add something like that. As time has gone on, both CISC and RISC systems have moved more toward a blend of both in-order to get the best of both worlds, from what i've heard interally most x86 chips actually work like a risc chip they just translate between things in the instruction decoder.

wmf2• 14 years ago

One definition of RISC is that every instruction should take one cycle and thus any instruction that takes longer is CISC. This led to MIPS not having multiply, for example.

A different definition is that RISC should not have any instructions that could be just as efficiently broken into multiple simpler general-purpose instructions. For example, a memory-register architecture can do a load-and-add in one instruction but RISC prefers separate load and add instructions that take the same time. In this view AES instructions are justified as RISC because implementing an AES round with multiple simple instructions is much slower (6x in Intel's case).

duaneb7• 14 years ago

You just described a CISC op.

klodolph• 14 years ago

> The one surprise in ARMv8, is the omission of any explicit support for multi-threading. Nearly every other major architecture, x86, MIPS, SPARC, and Power has support for multi-threading and at least one or two multi-threaded implementations.

What does this even mean? Are they talking about atomic operations? Hyperthreading?

enos_feedler3• 14 years ago

I think they are talking in the hardware sense: hyperthreading/SMT

duaneb7• 14 years ago

How much does that actually help? In my extremely fuzzy memory, it only worked out to around a 30% increase in ideal situations. I'd rather see them work on features that can be exploited with less voodoo.... like hardware 64-bit support, or SIMD support, or HTM, or hell, clock rate.

TwoBit• 14 years ago

I don't see how it could be about hyperthreading, since that's a CPU implementation detail and mostly unrelated to the instruction set. Maybe it's referring to specifying memory consistency behavior and support.

Symmetry3• 14 years ago

They're talking about stuff like the MIPS MT-ASE for instance.

http://www.mips.com/products/architectures/application-speci...

rblackwater6• 14 years ago

It looks like an interesting article, so it is a shame that it was split into 5 pages with no way to view everything on one page. I have no recourse but to not read the article at all.

smashing• 14 years ago

The article is hyperthreaded so you can read all five pages at once if your brain supports that kind of instruction set.

rblackwater6• 14 years ago

If only :/ I don't even have an FPU.

raverbashing• 14 years ago

Yes

too bad there's a 'fence' missing between each page

Or you'll just reread every page until everything makes sense since you can read things very fast for marketing purposes

dangrossman• 14 years ago

> I have no recourse but to not read the article at all

You could click the next button 4 times and read the full article. There's lots of content on each page. It would've taken 100% less typing than this complaint, and you would've spent that time learning instead of grumbling.

It's a real shame you can't read books either. Whole libraries of documents split into pages with no "view all" button.

rblackwater6• 14 years ago

There's a big difference in turning a page the size of your hand when you are already holding the book and trying to click a micro button the size of a word when you use the arrow keys to move the browser window.

I'll just wait until the exact same information appears on a single page. I was expressing sincere regret because I liked the first page, but I absolutely will not read paginated articles.

Also: you're obviously irritated by my grumbling, but grumbling about it is just a massive load of hypocrisy, so please realize I'm not going to be taking any of your comments all that seriously.

msh• 14 years ago

For the book there a a physical need to seperate it into pages, it would be worse to read one long paper scroll.

But webpages is easiest to read if its one long article, they just split it up to inflate their page view.

incision• 14 years ago

http://getpocket.com

It scrapes down and combines multi-page articles like this with a click for on or offline reading. Great interface and mobile apps too, I use it all the time.

rblackwater6• 14 years ago

I didn't know it did multiple pages. That's a great feature.

rogerbinns• 14 years ago

I wonder if it is possible to make the CPU be 64 bit only, and how much die space/power it would save by not including the 32 but cruft.

I'd also be curious if it was possible to software translate 32 bit arm binaries into 64 bit while retaining comparable performance.

lunarscape• 14 years ago

Honest question since I'm confused about terminology: Why is ARMv8 described in places as "backwards compatibility for existing 32-bit software" when some existing instructions will be removed in AArch64?

Symmetry3• 14 years ago

Because the ARM front end is so simple, it isn't hard to have multiple ones. One of these will be able to run existing 32-bit software.

Symmetry3• 14 years ago

A question about how HN works. I'd submitted the same article to HN at a much less opertune time so it fell off the "new" page before it got its first upvotes. [1]

Normally when somebody then resubmits the same article at a better time I thought they had to add a '~' at the end of the URL or something, but I don't see anything like that in this case. So how'd they do it?

(And I should say I'm glad that you all get to see this article, so thank you enos_feedler).

[1]http://news.ycombinator.com/item?id=4380604

parenthesis• 14 years ago

This submission has url http://www.realworldtech.com/arm64, yours has http://www.realworldtech.com/arm64/.

vdondeti• 14 years ago

Note that the article you submitted has a trailing /, this submission doesn't and so was not detected by HN as a duplicate story - or so it seems.

ARM Goes 64-bit

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