RISC-V Assembler: Arithmetic

https://projectf.io/posts/riscv-arithmetic/

by WillFlux • 2 years ago

72 47 2 years ago

WillFlux• 2 years ago

68000 is, in many ways, the pinnacle of assembler for programming, but RISC-V is pretty fun, too. I hope RISC-V tempts a few more people to try asm programming (again).

snvzz3• 2 years ago

I got into 68000 programming quite late (6yr ago), but I have been enjoying it (so far Amiga, Atari ST, rosco-m68k). It is a very programmer-friendly instruction set architecture.

RISC-V I started playing with more recently (early 2023, thanks to VisionFive 2), and it feels like my old favorite (MIPS), without the baggage MIPS carried.

It is a pleasure to work with this amount of GPRs and the comfortable alternative names for them that the official abi offers. I am loving it so far.

I expect to have RVA22+V hardware soon (Milk-V Oasis). Very much looking forward to playing with the vector extension on that.

sylware2• 2 years ago

Yep, same, I am keeping an eye on Oasis, but to run powerful GPU drivers (much user space would have to be ported from c++ to hand written risc-v assembly, SDK included). Don't rush it though, concurrent access and memory coherence of device memory is still not finalized.

I have been coding kind of a lot x64 recently, the limitation of 16 GPRs has been painful. I am sure that when I will crank up on rv64 assembly programming, those 32GPRs will feel like fresh air.

In the other hand, I am not fond of the ABI register names, and the pseudo-instructions involving mini-compilation. I'll stick to xNUMBER register names and won't use pseudo-instructions. Like I will avoid any abuse of the preprocessor.

throwaway712712• 2 years ago

I love RISC-V assembler.

I did a bit of x86 as stuff 20 years ago but hated it, now I wanted to teach my daughter some c and assembler and was thinking between arm and riscv, but riscv is just a joy to teach (I made a riscv assembler boardgame to help with the task https://punkx.org/overflow/)

Recently I was rewatching Hackers(1995) and I also got excited about the same quote:

“RISC architecture is going to change everything.” — Acid Burn

After spending some time with esp32s and riscv assembler, I think its more true than before :)

If you havent given it a try yet, there are many articles like the one, and also projects like https://luplab.gitlab.io/rvcodecjs/ or https://riscv.vercel.app/ where you can play with it, or even make your own emulator by learning from other emulators like https://github.com/OpenMachine-ai/tinyfive/blob/main/machine...

this cheatsheet is also very useful: https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/...

stockhorn• 2 years ago

Wow... Crazy this boardgame of yours. I'll definitly take a deeper look at this :). Thanks

throwaway712712• 2 years ago

thanks!

snvzz3• 2 years ago

Note this is an older (pre-ratification) cheatsheet.

You can tell because sbreak/scall. They are ebreak/ecall in the final version.

AIUI, the reason the name was changed is that they're not necessarily calls to the supervisor. E.g. they could be calls to machine mode, or the hypervisor. And some chips only implement M mode.

sylware2• 2 years ago

RISC-V, being an ISA worldwide royalty free standard, is meant for assembly writting. The main reason, above the "comfort" reason of C and similar, was ISA abstraction which has no meaning in the RISC-V realm. The middle ground is those very high level language interpreters (python/lua/ruby/javascript/etc) written directly in RISC-V assembly (without abuse of any assembler preprocessor, ofc).

I am currently writting my own rv64 on x64 virtual machine process, to code my programs in rv64 and not anymore in x64 in order to be "real hardware ready".

BTW, anybody knows a EU based distributor of milk-v duo boards with the cv1800 SOC (the one without ARM cores and a rv64 MCU) which I can contact using my domestic email server?

IshKebab3• 2 years ago

ProTip: Hexadecimal literals are prefixed with 0x.

I love the idea that someone could get to this page and not already know that!

Also this nicely highlights my pet peeve with assembly:

    add  rd, rs1, rs2  # rd = rs1 + rs2

It's very difficult to remember which parameter is the destination etc. IMO it would be much nicer if assembly had just a little more syntax for that sort of thing. E.g.

    rd = add rs1, rs2
    t0 = li 5

Just so the destination register is obvious. Ah well, nobody's going to do that. Assembly parsing is a total mess; there's no official grammar or anything - it's just "what GCC/LLVM do".

Findecanor2• 2 years ago

I love the idea that someone could get to this page and not already know that!

Might be worth noting because it is different in other assembly languages. In e.g. 6502 and MC680x0 asm, you'd first prefix with # to differentiate between an address (to load from and/or store to) and an "immediate" constant number, and then $ to denote hexadecimal. In x86 assembly (Intel style), you instead suffix the number with the letter h.

rd = add rs1, rs2

There are assembly languages for a few architectures that did/have that form or a similar one. Itanium assembly had instead the form:

    add r1 = r2, r3

JAlexoid• 2 years ago

Assembly is a language, that can be extended. Assembly++?

But at some point doing simple C makes more sense, than adding syntactic sugar to Assembly.

epcoa8• 2 years ago

there's no official grammar

Most architectures have something. Sparc had one (I still have the manual), PPC, 68k. I would even say x86 does as well but you can’t force its adoption, what AT&T and GNU wants to do on their own can’t be prevented. AT&T I suppose had the goal of making it all consistent, but I’m not sure if that was an improvement. Though I know of its vocal defendants.

RISC-V might be the exception more than anything, but they have a defacto syntax used throughout the spec.

Analog Devices DSPs and Itanium are examples with the = token.

http://laplace.physics.ubc.ca/vnp4/intel/docs/asm_lan.pdf

https://www.nxp.com/docs/en/reference-manual/M68000PRM.pdf

camel-cdr• 2 years ago

There is an assembly manual: https://github.com/riscv-non-isa/riscv-asm-manual/blob/maste...

jcranmer• 2 years ago

If you want fun, there's the x86 assembly syntax where the destination is the first register, and the x86 assembly syntax where the destination is the last register. One is the syntax as is used in official documentation (the Intel and AMD manuals), most reverse engineering tools, etc. The other is the syntax most commonly used in practice because it's what gcc defaults to and actually isn't documented (which gets into a problem when you start running into what gcc figured was the best way to adapt AVX-512 EVEX stuff into assembly).

So there's a lot of times where I'm staring at x86 assembly and going "wait, which version is this? the one that does destination first or destination second?"

epcoa8• 2 years ago

and the x86 assembly syntax where the destination is the last register.

ITYM AT&T :). The idea is that the basic grammar is common across architectures to help compiler backend authors. The historical reason for the ordering is because that’s how it was on the PDP-11, the “mother” assembly. And all AT&T/GNU versions preserve this ordering regardless of the vendor format.

The other is the syntax most commonly used in practice

It didn’t always used to be this way. In the dark ages before NASM, MASM was a top warez.

And depending on what you’re doing I don’t think Intel syntax is uncommon, gas will even accept it for the most part these days.

"wait, which version is this? the one that does destination first or destination second?"

There must be some mnemonic to associate sigil vomit with destination last. Shitty sigils come out the ass?

dvh• 2 years ago

Haystack needle

edgyquant2• 2 years ago

Assembly is meant to be 1:1 with machine code, which makes writing an assembler extremely easy as long as you know the architecture. Machine code doesn’t have things like equal signs, it’s literally just a series of bytes (an opcode and operands)

If you want equal signs, use C

epcoa8• 2 years ago

Machine code doesn’t have mnemonics either. What’s your point? There are assembly syntaxes with equal signs (The Itanium though ultimately a failure was not obscure and there are a handful of DSP ISAs that use this syntax). Not my cup of tea but your argument is specious.

Assembly is meant to be 1:1 with machine code,

And that is nonsense as well. RISC-V is a perfect example as it has plenty of pseudo ops. (Or do you actually think that the literal machine code bytes of an add instruction are 0x41 0x44 0x44? - they’re not)

Equal signs or not, macro assemblers have plenty of ergonomic conveniences layered above machine code.

How does an equal sign break any concordance with assembly and the underlying machine code anyway?

IshKebab3• 2 years ago

Nonsense. Machine code doesn't have things like commas, brackets and letters, yet we use those in assembly. There's zero reason why you couldn't do my proposal.

Also assembly mnemonics aren't even 1:1 with instructions. Pseudoinstructions do pretty much anything, and even something like `add` can assemble to two different instructions depending on the arguments.

As for writing an assembler being "extremely easy"... yeah no. There's no formal grammar so you're going to be reverse engineering LLVM and GCC's hilariously messy assemblers. Or more realistically, guessing and building an enormous test suite. Not easy at all.

Pet_Ant• 2 years ago

I mean if you want to be 1:1 with machine code, then don't look at the "J" Jump or "B" Branch instruction formats where the constant value is split into pieces and packed in around the registers.

With a '=' all OP is asking for is the wee-est bit of grammar (no more than in some addressing modes in CISC assemblers) and to change the order of the registers, which isn't crazy since immediates are already split.

https://en.wikipedia.org/wiki/RISC-V#Design

PS- while the instruction formats look crazy in isolation, there is a nice symmetry between them and if you start thinking about instruction decoding in discrete logic, they are actually quite an elegant design.

PPS- there is also “High Level Assembly” https://en.m.wikipedia.org/wiki/High_Level_Assembly

pjmlp• 2 years ago

TI has an Assembly language for DSPs that feels like coding in C in SSA form.

It is an Assembly with equal signs.

_a_a_a_6• 2 years ago

  >  rd = add rs1, rs2

I dunno, how about

  rd = rs1 + rs2

inkyoto3• 2 years ago

Because from the CPU perspective, «+» is ambiguous as there is not one «addition» but many:

- signed add

- unsigned add

- add and carry

There are a few others in other ISA', then there are the operand sizes (byte, half-word, word, long word etc) and the «+» operator does not capture the operand size nor the specifics whereas

- rd = rs1 addu8 rs2

makes the intention clear: «add the lower 8 bits from rs2 to rs1, don't set the sign bit when overflown and store the product in rd».

Moreover, the «+» operation is commutative and the CPU instructions are not, e.g.

- rd = rs + #10

and

- rd = #10 + rs

mean two completely different things for the CPU and the latter does not even have an encoding for it. The assembly processor is not the right place to place the smarts in to figure out the programmer's intention, either, as it is a very straightforward 1:1 assembly syntax to the ISA encoding translator.

lifthrasiir2• 2 years ago

That's a valid idea for RISC-V, but not always applicable. For example x86 `ADD` only accepts two operands, so `add rax, rbx` would add `rbx` to `rax` in place. `rax = add rax, rbx` would be a "faithful" translation, but `rax = add rbx, rcx` would be invalid (AFAIK there is still no three-operand version of scalar `ADD` in x86). `rax = add rbx` would be less redundant but way more confusing.

Another alternative is to mark the output in the operand position. Say, `add rd!, rs1, rs2`. I relate this to x86 `LEA` which is effectively an arithmetic operation but encoded like a load operation, hence a weird syntax `lea rax, [rbx + 42]` even though no memory access happens. Maybe that might be useful in the other way around.

LegionMammal978• 2 years ago

(AFAIK there is still no three-operand version of scalar `ADD` in x86)

Indeed, a 3-operand ADD is one of the extensions planned for Intel APX. But unless you need the output flags, an ordinary LEA suffices for adding two registers and storing the result in a third.

andromeduck• 2 years ago

I've been pushing to open source a VLIW assembler/codec generator with some syntax like this but alas may not stay long enough to see it through.

RISC-V Assembler: Arithmetic

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