Forth Inventor Chuck Moore's $20 144 core CPU now in full production

http://www.greenarraychips.com/

by csmeder • 15 years ago

271 93 15 years ago

csmeder3• 15 years ago

You can buy a 10 pack of evaluation chips from Green Array's web site or single from schmartboard's website http://www.schmartboard.com/index.asp?page=products_csp&...

kiba• 15 years ago

Let me get this straight: It's basically a microcontroller timed 144?

Can anyone explain to a nonhardware geek?

chalst• 15 years ago

This example gives something of an idea:

http://www.greenarraychips.com/home/documents/pub/AP002-OSC....

The picture I get is that the boundary between computing components and control/sensor electronics is dissolved.

zackmorris• 15 years ago

I've done many write-ups on this if you look under my profile. Basically the idea is that most of the big problems in software engineering can't be solved easily in a serial fashion with current methodologies, and many of the existing parallel solutions are either too expensive or two complicated to advance the state of the art. I wish I had this chip 15 years ago...

femto6• 15 years ago

It's the future, representing a convergence between Field Programmable Gate Arrays (FPGAs) and the microprocessor.

Gate arrays are vast arrays of logic gates, which can be wired together in almost arbitrary patterns by a sea of "fuses", typically controlled by state stored in on-board SRAM. They are real time and blindingly fast due to their massive parallelism, achieving supercomputer type speeds when applied to the right type of problem and programmed well. They are more difficult to program than a microprocessor. One way of looking at an FPGA is as an array of tens of millions of very simple computing engines.

Over the years, the number of transistors on an FPGA has been rocketing up. Generally these transistors have been put to use by providing more and more simple logic blocks. We are now to the point where we have almost more gates than we know what to do with, and the chip is being dominated by interconnects. This has seen a move towards including a limited number of elaborate hard wired blocks, such as CPUs and multipliers, in addition to the array of logic.

The logical evolution is to stop providing more blocks, but make each block more complex as transistor counts go up. Eventually we will see arrays of tens of millions of microprocessors, rather than tens of millions of logic blocks. There will be no distinction between a multicore CPU and FPGA.

It's worth noting that the first Xilinx FPGAs, thirty years ago, provided arrays of around 144 logic blocks, similar to the processor count in this chip. Extrapolate 30 years and we will have an array of 10 million microprocessors.

femto6• 15 years ago

Correction: I've been lax in my terminology with logic gates and cells. Current big FPGAs contain around 2 million "logic cells", which typically represent between 1 and 10 logic gates each, depending on device programming.

sliverstorm7• 15 years ago

Unfortunately for the FPGA guys, it seems like in general the closer they get to CPUs the less compelling their product becomes.

VladRussian• 15 years ago

>We are now to the point where we have almost more gates than we know what to do with,

limits of von Neumann architecture (and its underlying mathematics of recursive functions) as a mental framework for our thinking about computing.

neopanz3• 15 years ago

Love the guy and his passion for its chips, but this 144-computer chip looks like a solution in search of a problem: what is trying to solve? How's the inter-core communication handled? On the other hand, creating weird chips like these, just because you can, is awesome and stimulating a hacker's mind.

101001010111• 15 years ago

Not sure if it's a legitimate "problem" or not, but how about the availability of single chips, or 10-packs?

Assuming someone wanted to produce a prototype board, but didn't want to purchase 1000's of CPU chips, are there many CPU chip makers who offer low quantities like this?

swdunlop• 15 years ago

It appears that CM's intent with the F18A core is to create an extremely low power processor that scales the number of cores to the complexity of the problem being addressed -- look at the reference sheets about what the requirements are to maintain core states.

The design makes more sense when you stop trying to think of it as an ARM or AVR competitor, and more like a replacement for FPGA's.

6ren2• 15 years ago

Some of the industries greatest advances have began as a solution in search of a problem, such as the microprocessor (which its inventor, Intel, didn't think much of compared with memory chips where the real money was). Most fail of course.

If someone can make many-core, in this form, do something useful that can't be done elsewhere (unlike DSP and GPUs, which are already many-core), it will fundamentally upend computing.

queensnake2• 15 years ago

> greatest advances have began as a solution in search of a problem

.. and the laser(!)

neuraxon772• 15 years ago

"Between nodes there are 18 bit, bidirectional parallel buses called Comm Ports. The handshaking on these ports is trivially simple and the latency and jitter are low, on the order of gate delays, tens of picoseconds. When a node is reading or writing a Comm Port, it proceeds with no delay if its partner is ready to transfer data. If the partner is not yet ready, the node waits until it is. While waiting, a node’s power consumption drops, within picoseconds, to nothing but leakage. When the partner becomes ready the idle node resumes its work within picoseconds."

http://www.greenarraychips.com/home/documents/greg/WP002-100...

rbanffy2• 15 years ago

> what is trying to solve?

Don't picture each core running C programs. Think the whole chip replacing something you would use an FPGA for, but more flexible, capable of adjusting its own behavior according to the environment.

neopanz3• 15 years ago

I think the only thing Chuck is missing is a few 20-somethings hackers, bent on solving an 'impossible' problem with his chips.

csmeder3• 15 years ago

That's why I'm posting it here.

Some possible ideas

====================

- Sound processing (think 144 cores preforming Fourier Transforms)

- Pico Satellites (This chip has a surprisingly extreme low power requirement).

- Wireless communication (small power requirement means small batteries)

- Computer Vision processing. Imagine toys or tools that can process visual information faster than an Xbox.

- Basically anything that can be done in parallel, that is suited for small size and low power, but doesn't require much on chip memory.

ippisl2• 15 years ago

Had a rough look on it's instruction set and didn't see anything resembling DSP instructions. So i'm not sure it would be great for all those uses.

On the other hand, picochip sells a 200-300 core DSP , that is being used for the wireless industry.

pixelcloud• 15 years ago

I really hope these have a good application for DSP. I can imagine the sweet homebrew synths that people will be coming up with.

femto6• 15 years ago

GNU radio

Poyeyo• 15 years ago

Video-games?

Can this replace a physics dedicated processor? What about latency?

neopanz3• 15 years ago

May be if you use 100+ of these (~14400 'computers') you can build a machine with emerging behavior, brain-like?

ypcx• 15 years ago

I knew it. The name "Moore" sounded suspicious to me immediately. Now I know his real name is Chuck Testa!!!

On a more serious note, what we need much more of is not the processing speed. What we need much more of is what I call "memory processability", which roughly means "how many times per second can you process the whole memory" - or something like that. Basically how much CPU is there per RAM. Indexing is a great hack, but a hack it still is. Memory and processing cells must be merged into a single, massively parallel chip.

thisrod• 15 years ago

That was done in the 80's: http://en.wikipedia.org/wiki/Connection_Machine . Richard Feynman had to help the designers with the hard bits.

Users recall them fondly. In the end, clusters became too cheap for custom hardware like this to compete.

itsameta4• 15 years ago

>What we need much more of is what I call "memory processability", which roughly means "how many times per second can you process the whole memory"

I might be misinterpreting, but I think the phrase you're looking for is "memory bandwidth".

sliverstorm7• 15 years ago

If 15,000 computers was all you needed for AI, we'd have it by now. Major datacenters have way more machines than that, which are far more powerful than a milliwatt microcontroller to boot.

scottyallen• 15 years ago

Not being much of a hardware geek, I'm having a hard time evaluating how fast each core is.

From the site: "With instruction times as low as 1400 picoseconds and consuming as little as 7 picojoules of energy, each of the 144 computers can do its work with unprecedented speed for a microcontroller and yet at unprecedentedly low energy cost, transitioning between running and suspended states in gate delay times. When suspended, each of the computers uses less than 100 nanowatts."

How does this instruction time compare to other modern processors?

It sounds to me like some of the benefit to be had here may be from the low amount of power necessary per core. Power and associated cooling is a MAJOR source of cost for datacenters, and so if this really is a significantly lower power consumption (again, I don't know how much power the alternatives use), then it could have a big impact on the cost of commodity computation power.

_delirium• 15 years ago

If 1400 picoseconds is the time it takes for a clock cycle (and therefore the minimum instruction time for 1-cycle instructions), that'd be about 700 MHz, which actually seems pretty high compared to what I would've guessed.

neuraxon772• 15 years ago

As far as I know, the cores aren't clocked. Instead Chuck designed his own transistors using his own OKAD II VLSI tools to be efficient on the CMOS process node with switching speeds being dictated by the transistor type and interconnect electrical properties, then designed the cores so that they're only switching those transistors when they do actual work.

dkersten6• 15 years ago

instruction times as low as 1400 picoseconds

As a random comparison, that's 1.4 nanoseconds per cycle. The PIC24H 16bit PIC microcontroller form Microchip runs at 40MHz, making it 12.5 nanoseconds per cycle. Now, I don't know enough about Chuck Moore's processors and haven't read the docs yet, so I don't know, for example, how many cycle a typical instruction would take, or how much work it takes to synchronise cores, but assuming 1 cycle per instruction, that would make these 144 core $20 processors 8.9 times faster per core. I know its not realistic to assume linear performance speedup from additional cores, but if we do 144 things at once, this makes them 1285 times faster than the PIC24H microcontroller, yet these processors only cost 4 to 6 (depending on amount of RAM) times the cost of a PIC24H microcontroller.

Note that the PIC24H microcontrollers are the more expensive, high performance (but not the highest) model of Microchips 16-bit PIC microcontrollers.

ChuckMcM• 15 years ago

Well if you ever wanted to be 'out there' Chuck's processor would be a great place to start. Chuck Moore invented Forth and has been building machines that can run Forth efficiently for years. Think of it as a Turing machine that can do useful work. He has pushed the edge of computation per watt for years.

That being said, I've heard him talk about this chips for years and it is great to see it finally see the light of day. If you were familiar with the Transputer technology, this is a better take on that, if you are familar with FPGAs you can think of it as an FPGA with processors instead of CLBs.

Things that it can do are similar to what Intel is doing with Larrabee or some of the CUDA stuff that nVidia has done. It doesn't have a GDDR3 interface to a GB of memory so you can't custom build your own GPU, but you could do your own PhysX type engine with it.

It also makes a helluva differential cryptanalysis tool, or a signals analysis tool in general.

6ren2• 15 years ago

CLB = configurable logic blocks

joelthelion• 15 years ago

It might make a good bitcoin mining platform?

iwwr• 15 years ago

Not really, it's underpowered and mining lends itself better to vector-oriented processors (like GPUs) rather than CPUs.

zhazam• 15 years ago

At $20 you'd only need a single decade to make up the costs :)

pnathan2• 15 years ago

I have done my Master's work with the XCore (xmos.com), which is a direct descendant of the Transputer. It's programmed in an C-with-CSP-constructs called XC.

I found it very easy to write XC correctly. I think that the CSP/transputer idea is really the best way for most parallel programming to happen. MPI and pthreads allow more flexibility, but in most (say, 80%) of cases, that's not needed for your application.

watmough• 15 years ago

I believe the Go model is based on CSP.

A cursory look at Go reminded me of some time I spent writing OCCAM code.

protomyth• 15 years ago

The Propeller chip http://www.parallax.com/propeller/ is another embedded market chip in the same vein although nowhere near as many cores. Having something like this make for some interesting embedded designs.

Also, check the site for the arrayForth stuff.

On another note, it would be interesting if something like these existed in the 64-bit size. Larrabee is interesting, but if it was a simpler stack machine at around this price point then perhaps some work could be done on different ways to do parallelism.

ippisl2• 15 years ago

Tilera does a 64-bit CPU with 64/100cores.If they would offer access to it using a pay-per-hour model, that would be interesting.

dkersten6• 15 years ago

I spoke to one of the Tilera guys a few years back about evaluating their boards for use in a telco project I was working on at the time, but gave up because I wasn't prepared to drop $15K on a development board just to evaluate it.

The technology itself was extremely interesting, though, and would probably have been a good fit for what I was doing. Also, the cost of the dev board included technical support and from speaking to the guy, I got the impression that they actually help you port your code to their platform.

rbanffy2• 15 years ago

Wondering if it ciuld emulate an Apple Ii in real time and, within it, run GraFORTH.

jxcole• 15 years ago

I think this sounds ridiculously cool and at $20 I could probably afford to play around with it. But I have no knowledge of hardware, just programming. To me chips just look like thin green rectangular prisms. How would I get it to actually, you know, do stuff?

ars• 15 years ago

You would probably want to buy the Evaluation Board which lets you control the machine using USB ports and an ASCII console.

The thing is, it's just a computer. The real value of this is hooking it to hardware to actually do something. So I suggest starting here instead: http://www.greenarraychips.com/home/documents/budget.html and learning how to work with hardware as well.

makmanalp• 15 years ago

you can do this for about $30: http://www.greenarraychips.com/home/documents/budget.html

"suggestion for a complete system"

defen• 15 years ago

Call up Woz, I hear he was good at that stuff.

sausagefeet• 15 years ago

Is this something I would use in the place of something like an Arduino (for example, putting a brain on an RC car)?

Symmetry2• 15 years ago

In past Forth threads I've complained the the Forth model for a computer seems just too at odds with how modern CPUs actually work for me to want to learn it. Well, I look at this thing and its like the soft draft of the future slipping underneath the door, whispering that maybe I should learn Forth after all.

dkersten6• 15 years ago

Its worth noting that a number of popular VM's, eg, the JVM, have Forth-like stack-based instruction sets.

derleth2• 15 years ago

OTOH, LLVM is, if anything, a register machine, so as to better map to the register machines we're implementing in hardware right now.

_sh• 15 years ago

> maybe I should learn Forth after all

http://factorcode.org/

Make it easy on yourself.

wx77• 15 years ago

That is probably making it harder on yourself as the recommended route for learning factor is to read a forth book and read the factor docs. (Unless something has changed and a book or big tutorial has been written)

With that said, Factor is really cool.

ww520• 15 years ago

What are the software stacks that are available on the chip? Forth must be there. Anything else?

mung7• 15 years ago

This is all new to me. Does anyone know if these chips could be used for bitcoin mining?

However, I believe you would have to write completely new programs if it is possible.

Don_Wallace• 15 years ago

Imagine a Beowulf cluster of those.

thesz4• 15 years ago

I certainly should voice my opinion here.

I've done analysis of GA144 before: http://news.ycombinator.com/item?id=1810641

Most of the Chuck Moore design (I reviewed several, starting from M17) can be described by quote from Devil Wears Prada: "the same girl- stylish, slender, of course... worships the magazine. But so often, they turn out to be- I don't know- disappointing and, um... stupid". Chuck Moore designs are all slick, slender, stylish, worship Forth, but they turn out to be disappointing and stupid in the end. The only beneficiary often is Chuck Moore itself. You just cannot apply his experience to other places in the world of computing.

Let's see what we have here in GA144.

The memory inside all cores is way too small for general purpose programs, even if you split your program into 144 parts and spread them across cores. 64 words of RAM, ie, 128 bytes. 128 bytes times 144 - 18Kbytes. Same for the (program) ROM, and you should factor communication code in there. Communication cost affects RAM as well.

They offer no compiler from high-level language like C. You had to learn a specific dialect of Forth and some bizarre (albeit small) assembly language.

The only benefit for general population from this affair is the relative ease of the desing of asynchronous hardware.

http://en.wikipedia.org/wiki/Asynchronous_system

bitcracker2• 15 years ago

Your are focusing on classic applications only.

The GA144 is so different from the classic way of computing that it requires new approaches of development. One very interesting feature of GA144 is that all 144 cores can share instructions over I/O lines. That means every core can send instructions to their neighbors who execute them directly without conversion.

I/O ist fast enough. I guess it should be possible to have (someday) an external interface to SRAM which circumvents the low memory problem.

> They offer no compiler from high-level language like C.

That's right, and that's the real weak spot of GA144. Almost every microcontroller board today comes with C or alike. Mr. Moore loves Forth but I doubt that there are many developers out there who like to be forced to learn Forth just for this single platform. I know Forth, it was one of my first languages I ever learned. It is perfectly suitable for embedded systems but you have to learn a lot to master it.

thesz4• 15 years ago

I protyped dynamic dataflow machine which (in theory) could be scaled to hundreds of cores (corelets - something very small which does not have even jump command). In my experiments readying information to be sent accounts for hefty 30%+ of code.

http://thesz.mskhug.ru/svn/hhdl/previous/HSDF/CoreletTest.hs

The link above contains some simple "Hello, world!" program, in five "big instructions" which contains 21 corelet instruction in total. 8 of those 21 instructions are send and front advancing instructions - their only purpose is to establish communication between program parts. My machine sends pointers to "big instructions", up to 32 bytes long (up to 32 instructions if you're lucky) while GA144 could send only 4 instructions max.

30% of 4 instructions is 1 instruction. Another one instruction from those 4 is a loop or jump or something like that. So you have two instructions to perform program logic. And this is best case.

So I again express dislike of GA144 as a computing machine. And I again express my gratitude to Chuck Moore for proving that clockless design works.

honkybozo• 15 years ago

Glad to see this thread. G144A12 does better than you'd expect for 18 bit ALUs doing 32 bit circular shifts and adds, but that costs enough extra instructions that for this particular algorithm at any Bitcoin-useful combination of throughput/energy/cost we can't compete with the genuine 32-bit ALUs of the bigger ATI GPUs. Ya can't be perfect for all problems all the time :) Nevertheless we'll be posting an app note eventually on SHA256 as an illustration of techniques in pipelining. The $20 price is for small quantities. Standard exponential decay curves apply for production quantities; we want to see our chips in people's products and are priced to encourage that. As for 20 somethings, nobody in our company gets a paycheck (yet) so someone has to be willing to work for nothing, but if you have a practical idea for an app note and want to work with us to get it done and published please email greg at greenarraychips dot com and let's discuss it. Thanks for your interest, folks - Greg Bailey, GreenArrays, Inc.

Forth Inventor Chuck Moore's $20 144 core CPU now in full production

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