GNU Assembler Patches For Optimizing The Intel Jump Conditional Code Erratum

https://www.phoronix.com/scan.php?page=news_item&px=GNU-Assembler-Patches-JCC

140 37 7 years ago

atq2119• 7 years ago

The headline feels a bit too click-baity, but this really is serious stuff.

One of the most fundamental instructions of x86, the Jcc conditional jump, can apparently be executed incorrectly by most Intel CPUs out there.

What's worse, part of Intel's strategy for mitigation is to push compiler toolchain changes that, if deployed as they desire, will punish the performance of everybody on x86, including those who are using unaffected processors (cough AMD cough).

smitty1e• 7 years ago

This is why we must protect our right to bear ARMs.

cesarb3• 7 years ago

ARM is no better. One of the most popular ARM boards (the Raspberry Pi) uses a core which is affected by an errata which also needs a workaround on the assembler/linker. I don't have my RPi with me at the moment, so I don't know the errata number (it's one of the two printed by the kernel during boot).

damageboy• 7 years ago

OP from twitter here. I'll take the blame for the click-baity-ness, but I was really shocked and this was in real-time in my defense.

I'm assuming it will get resolved, as the errata suggests by shoving lots of 0x2c segment overrides to re-align those jumps.

The price won't be 0, but will definitely less than the very extreme 20% edge case I stumbled upon.

I'm more "worried" or annoyed by older binaries that will never get updated. But hey... (；⌣̀_⌣́)

chris_overseas• 7 years ago

For those not understanding the context of the parent's comment, this HN post originally linked to @damageboy's https://twitter.com/damageboy/status/1194751035136450560 tweet showing a 20% performance hit, but was later changed by mods to link to the phoronix.com article.

icebraining• 7 years ago

I wonder if it'll start making sense to ship different binaries for Intel CPUs.

bArray• 7 years ago

It'll confuse the hell out of people, but I think it's probably the way to go. I hope for example that Linux based package managers split the "amd64" so that we all don't get hit by this crap.

my123• 7 years ago

If only the microcode workaround affected just Jcc...

The MCU prevents jump instructions from being cached in the Decoded ICache when the jump instructions cross a 32-byte boundary or when they end on a 32-byte boundary. In this context, Jump Instructions include all jumptypes: conditional jump (Jcc), macro-fusedop-Jcc(where opis one ofcmp, test, add, sub, and, inc, ordec), direct unconditional jump, indirect jump, direct/indirect call, and return

These patches are just to recover some of the performance penalty...

cesarb3• 7 years ago

including those who are using unaffected processors (cough AMD cough).

A more recent Phoronix article ("Intel's Assembler Changes For JCC Erratum Are Not Hurting AMD", https://www.phoronix.com/scan.php?page=news_item&px=AMD-With...) says otherwise.

stefan_• 7 years ago

Instead of another fucking Twitter thread, just read the article from Phoronix from yesterday:

https://www.phoronix.com/scan.php?page=news_item&px=GNU-Asse...

saagarjha3• 7 years ago

This one has numbers in it, though.

rwmj• 7 years ago

Here's a cryptic Intel whitepaper: https://www.intel.com/content/dam/support/us/en/documents/pr...

tlamponi• 7 years ago

Not sure what's worse, Twitter or Phoronix though..

just link the patch submission itself: https://sourceware.org/ml/binutils/2019-11/msg00173.html

executesorder66• 7 years ago

What is the purpose of "censoring" the word shitstorm, if it is undoubtedly obvious which word you meant to the point that it makes no difference either way?

Or to phrase my question differently:

  Wh*t is t*e pur**se of "cens*ring" th* w*rd sh**storm, *f *t is u*doub*edly ob*ious wh*ch wo*d y*u me*nt to t*e poin*t th*t i* mak*s n* di**erence ei*her w*y?

grzte• 7 years ago

Americanisms. Like how European reality shows are starting to bleep expletives when that's complete unnecessary here.

bil7• 7 years ago

seems to me like you are questioning the whole concept of censoring expletives

chongli• 7 years ago

I think the GP’s point is this: if you’re against the use of an expletive, then don’t use it. Putting it behind a fig leaf is embarrassing and silly.

lidHanteyk• 7 years ago

Sure, Bowdlerization is harmful. It is a lossy transformation, it doesn't protect children, and ultimately the only people protected are the sort of people that don't want other people to be free to explore the world, leading to censorious and stifling behaviors.

platz• 7 years ago

I don't appreciate the aggressiveness and clear attempt to induce outrage with the title. This is the outrage algorithm working.

* Edit - the previous title referenced a Twitter thread, not phoronix. The new title is fine.

omnimus• 7 years ago

I do appreciate it. Its quite serious.

giomasce2• 7 years ago

I am not really following the details, but it seems that Intel is taking a blunder after the other. Will we ever able to trust their CPUs again?

orbital-decay• 7 years ago

We have been able to, and pretty quickly, after the F00F and FDIV bugs.

giomasce2• 7 years ago

Yeah, but those two were two isolated issues in a decade. Now we're having a continuous stream of microarchitectural bugs that require more and more complicated fixes in toolchain, kernel and microcode. I am an outsider, but the impression is that the thing is exploding.

mmastrac• 7 years ago

This was pretty terrible. I wouldn't be surprised if this was responsible for a good number of heisenbugs on a few platforms.

Not only can you not use a jump instruction ending or crossing a 32-byte boundary, but you can't use a "macro-fused" pair of instructions like cmp+jump! [1]

The fix is _relatively_ simple [2] on affected platforms as they will likely be able to pad an appropriate level of NOPs to avoid that boundary before emitting a problematic set of instructions, but you will be taking a perf hit equivalent to losing a bunch of cache memory to useless NOPs and a (likely small) amount of power/time to skip those NOPs in the instruction stream.

Where this gets ugly: people shipping binaries will have the choice of mitigating this for everyone (padding out code+small perf impact on non-affected platforms) or hitting a very slow code path on affected systems.

[1] https://www.intel.com/content/dam/support/us/en/documents/pr...

[2] Edit: the recommended fix from the whitepaper appears to be padding out earlier instructions via a "benign" prefix rather than adding NOPs.

lousken• 7 years ago

Intel is becoming a meme with those 30-50 page erratas in their documents. When they can't improve IPC or nm tech why don't they at least focus on fixing bugs?

raxxorrax• 7 years ago

Well, if they fix this bug the hardware will become slower in any case. Honestly I don't understand the issue and wonder why it didn't manifest constantly.

unpredictable behavior could happen when jump instructions cross cache lines

Under which kind of circumstances? What does it mean anyway? The jump-instruction itself with arguments crossing cache lines? Wouldn't that happen quite often?

GNU Assembler Patches For Optimizing The Intel Jump Conditional Code Erratum

Related Stories