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There are also many high-performance Chinese implementations that are open-source (e.g., XuanTie C910, XiangShan, etc.).

While achieving an open-core design comparable to Zen 5 is unlikely in the near term, a sustained open-source collaborative effort could, in the long run, significantly change the situation. For example, current versions of XiangShan are targeting ~20 SPECint 2006/GHz (early where at ~9).

This is going to end badly — and soon. It’s ironic that catastrophic forgetting (i.e., the inability to perform continuous learning) and hallucinations (i.e., the failure to recognize when a prediction is unfounded) won’t be the causes of the crash, but rather greed and stupidity.

As far as I know, pruning is related to age. At birth, we have a massive number of silent synapses. As we grow older, those that remain unused (i.e., inactive) tend to disappear. This process involves a delicate mechanism, including components of the immune system.

The unfortunate reality is that no one truly understands how memory works. Many theories are floating around, but the fundamental components remain elusive. One thing is certain: it is quite different from backpropagation. Thankfully, our brains do not suffer from catastrophic forgetting.

The usefulness of AST is not limited to biological systems. A hypothetical conscious electronic system might also need AST to: (1) stabilize internal states more quickly during learning, (2) respond more quickly to input stimuli, (3) use internal predictive flows to 'simulate' inputs in order to learn from a reduced number of sensory-linked events.

It may not magically appear. It may, by design, be woven into the learning process.

I wonder what will happen if someone figures out that fused FP mult add is no longer needed (e.g. just count spikes and add subtract permanence). This could be a big problem for the guys with all their eggs in one basket (like NVIDIA).

Box64 and RISC-V 3 years ago

We need RISCV hardware with Ztso extension to shine here. Enforcing Total store ordering (TSO) over a release consistency (RC) memory model is otherwise a pain. I don't know if Dynarec is tackling this problem (or just focusing emulation on single-threaded software).

The first hypothesis seems to be false. We have no idea how the brain works or how conscience arises (and what it is). So how can we reproduce or surpass it with a pattern recognition machine like a DL system? Just because the brain uses pattern recognition as a trick to build a model of the world does not mean that DL magically produces conscience. There is too much evidence that biological systems don't work that way, and all this discussion seems like old alchemists discussing whether gold transmutation could destroy the world. We have to learn "chemistry" first. Later we can start discussing that (or deeper issues like what will be the relationships between us and sentient pieces of silicon).

I wonder why they don't start to use secure enclaves to fix this cheating debacle? This might solve the problem for good. Between the cheaters and the companies trying to stem the tide, is destroying FPS online gaming.

I guess intel SGX chaos didn't help either.

How many uOps is that instruction in x86_64?

Note that while the performance effect of L1I cache misses is negligible, the complex x86-64 decoder may not be. Some SPECpu2017 have front-end problems due to the x86-64 decoder.

Especially when, like this tool, the guy starts calling home 5 min after start (attempt caught by LuLu without taking a single screenshot). Supposedly is only performance and usage metrics,... but who knows.