tfmkevin

There are no separate tools for military use. And, the mil/aero versions of the chips are usually a generation or two behind because of the extra work to make them high-reliability, produce the required documentation, etc.

HLS is real. I've talked with dozens of teams who have successfully used HLS tools such as Mentor's Catapult, Xilinx's Vivado HLS, and Cadence's Stratus for a wide range of ASIC and FPGA projects. They claim they saw compelling benefits in project schedules, architectural flexibility, and overall performance. However, HLS is still (IMHO) a "power tool" for competent digital designers, not a tool that enables a software designer to create hardware. There is too much hardware-specific expertise required to create good HLS-able code and to do the tradeoffs like pipelining, unrolling, memory architecture, etc etc etc.

The "average person" cannot program for it. I've managed teams as large as 60 extremely competent full-time EDA engineers working for years on only the synthesis portion of the problem. It is FAR more complex than, say, developing a compiler. Both Xilinx and Intel have more engineers developing FPGA software tools than they do developing FPGA hardware. It's a common misconception that just any group of competent software engineers could whip out better FPGA tools if they only had access...

Nope. Reconfiguration takes milliseconds. Also, Arria 10 supports partial reconfiguration which means that the FPGA can keep operating while some of the logic is reconfigured via bitstream.

Wally Rhines of Mentor Graphics recently discussed the need for simulation testing for autonomous vehicle systems. He quoted the CEO of Toyota as saying that 9 billion miles of testing would be required, and pointed our that would take 300 cars, driving 60 miles per hour, 24 hours a day for 50 years. He argues that the only way to achieve that level of testing is (therefore) simulation.

The problem is that we have designed ourselves into an architectural cul-de-sac when it comes to processors. We have fifty-plus years of evolution on programming methodologies built on top of von Neumann architectures. Moore's Law has given us decades of exponential gain without significant challenge to that architecture, and now that Moore's Law is reaping diminishing returns in terms of compute performance we are in the situation where we'd have to go backward forty years on our programming model in order to take advantage of a superior (given today's technology) architecture. For example, FPGAs can in many cases outperform von Neumann machines by orders of magnitude in terms of compute performance and (more importantly) performance per watt. However, the programming model and ecosystem for FPGAs is worse than primitive. Something you could write in a couple hundred lines of C code could take months to get up and running on an FPGA. We need a way to transition from von Neumann computing to alternative architectures without starting over on computer science. Or, perhaps recent trends in neural networks will eliminate the need for that?