tcherasaro

Fair points. I think my point about people targeting search overlaps actually.

Creators think they can't survive on 2k views, especially since that's not guaranteed and YouTube isn't providing actual search results all the way down the SERP providing even less opportunity to rank so then they go after more views with clickbait and engagement across broader topics that aren't going to meet a users search intent and provide specific content. In a lot of niches that might be true.

Now if they could knew they could consistently rank in search and that multiple videos producing 2k views per month, month after month and compound after time then they might have more interest in optimizing those videos more.

Im a big fan of Rossmann, and wouldn't you know I found that video you are talking about on YouTube search of all places by searching "louis rossmann creating website with gemini"

Thanks for the suggestion. I'll check that out.

I've certainly experienced both of these and a lot of the other occurrences people are describing here, but here's what I think is going on in these 2 cases and why. This is based on my own observations actually trying to get videos ranked in search.

Immediately after publishing a search optimized video the main way I measure if I was successful with the technical part of optimization (Title, description, transcript, Text Overlay, keyword density) is to search the exact title to see if my video appears. Immediately after publishing like within minutes, it usually does appear within the first five to ten results.

After the youtube "testing period" if the CTR and AVD (retention) are good, then the views increase from there as the video starts to rank and get tested for more related keywords. And the video certainly continues to rank for the exact title.

If click through and retention are bad in the testing period then the video fails to rank and the video seems to disappear or get pushed way down when searching exact title.

So I believe CTR and AVD maybe factors in YouTube SEO.

After 3-5 results I have noticed that there seems be a segment of long form videos and then shorts actually targeting that casual browse traffic in a search result page! The long form results in those positions are usually weak on technical optimization, only tangentially related or fluffy in terms of delivering on the user's search intent, but from larger channels that are heavily edited, produced and optimized for click through and viewer retention. The kind of hostile user experience that tries to keep people watching for longer with retention editing and by teasing or hyping good info when the user really just needs answers but are easily enticed by better packaging when the first 3 results didn't meet their intent.

I notice the same videos again and again in those positions for a wide range of primary keywords and even the seed keyword, and they get tons of search traffic even though they aren't answering user intent because youtube has realized these videos are effective at converting a laser-focused search user looking for specific information into a casual viewer who is happy to be entertained for a longer period of time when they couldn't find the information they were really looking for.

Let's face it, if the first few results didn't deliver, weren't optimized; then from YouTube's perspective, the user is browsing at that point and it's going to do it's best to retain them.

Potentially unpopular idea:

Maybe YouTube search is so bad because videos are poorly optimized for search.

Today most of the emphasis to creators on YouTube is to create content that targets browse traffic and shorts to go viral and get millions of views.

Not so much videos targeting specific user intent with a term that might get 2k views per month if it ranks #1.

Yeah and this is probably why they said in the article:

“ And under the hood, EmDash is powered by Astro, the fastest web framework for content-driven websites.”

Yeah, I used to use Virtualmin and webmin 10 years ago. Looks just like em!

This guy is so preoccupied with whether or not he COULD manufacture his own guided missile, he didn’t stop to think if he SHOULD.

Of course he could, anyone can these days. So the most important question is the latter.

Nice computer “racks”

LOL exactly! That's why I want to build something like this: https://x.com/TroyCherasaro/status/2016767340457980403

Yes, I have 2 candidates so far: - A 7-inch OLED (that's 1920 by 1080) - A much cheaper but still nice IPS display. Again, 7-inch I'm not sure where I'm going with this yet, but if other people want one, I want to have some flexibility in the specs and pricing for people to select from.

I've been meaning to make a post about this on X for some time, so I went ahead and did it tonight. If you want to head over there and see the renders of what I'm thinking: https://x.com/TroyCherasaro/status/2016767340457980403

I am planning to build something similar as a hobby project except my idea is that Claude Code runs everything on the device for you.

Reminds me when I was working on the video system for a mast on a sub-marine 20 years ago.

Customer had impossible set of latency, resolution, processing and storage requirements for their video. They also insisted we use this new H.264 standard that just came out though not a requirement.

We quickly found MJPEG was superior for meeting their requirements in every way. It took a lot of convincing though. H.264 was and would still be a complete non-starter for them.

Classic. Due for another read to see how it’s holding up in the AI era.

Art of deception in full effect here. Kevin Mitnick would be proud.

Another day, and another smart person finally discovers the benefits of leveraging AI to write code.

I remember some of those.

I can supply my own anecdata here.

I recently went through 6 weeks of PT for injured tendons / tendinitis in my arms with 0 results.

The therapist suggested we try dry needling + electric stimulation for another 6 weeks. So we did that and I recovered 90% in the second 6 weeks of therapy.

There were side effects but they were minimal and completely gone now.

It looked a little like this except on my arms:

https://youtube.com/shorts/pTEPMgDdy2A?si=MSx7YnmUbApsigWe

I was skeptical but sold on the benefits and relieved to have an effective therapy option to fall back on when it happens again as it does every couple years. Unfortunately, my insurance doesn’t pay for it.

This setup reminds me of “Snow Crash” that Neal Stephenson novel.

As one of the “skilled electronics engineers” in the US you could count on US soil (whatever that means) I can tell you this article reads very strangely to a EE.

“we were able to take all those designs and spin up our own SMT, it's called Surface Mount Technology”

“run that through our surface mount technology by our line operators”

“meaning the printed circuit board or PCBA assembly”

So, he’s definitely not an EE. No EE talks like this when they are trying to explain the nuts and bolts to a lay person. Either that or the editor took liberties they shouldn’t have.

I had undergraduate and graduate courses that studied x86 at 2 different universities.

Hi, @Timot05. I’m a former EE with 20 yrs experience working in the industry and have designed dozens of very large complex mixed signal PCBAs 4-32 layers, as well as about the same number of large FPGA SoC designs.

I watched the demo video out of curiosity and here’s my 2 cents, though there is a lot to unpack here:

First if you want to know the current state of “how does git look like in hardware” as far as PCBA design is concerned look at Altium which uses git under the hood now to provide a very nice visual way to show differences in both the schematic and PCB layout between versions that solves some real pain points for an EE and therefore EEs actually want it and use it. There are ways to create reusable, version controlled sub-circuits that get put into libraries as well:

https://www.altium.com/altium-365/hardware-version-control https://resources.altium.com/p/introduction-git-altium-desig...

Whatever open source you build should be modeled after that.

I found the above very nice after years of manually using git to version control PCBA designs developed in other ECAD tools like PADS, Orcad, Cadence etc. I even tried to get a couple EE’s and layout people to use my methods of git version control, documented in the README of course, but to no avail, most strictly hardware EEs (with no FPGA or SW background) either can’t grasp git or don’t see the point in spending the time on it. The same people will quickly pay $10k-15k a seat for Altium to get that slick UI on top of git version control because it makes things more visual, not less, which as others have mentioned is important in PCBA design I’ll get to in a second.

But, I understand better what you actually mean because you phrased it another way “how can groups of people coordinate and share their work in hardware?”

That depends of course how / who are you coordinating and sharing with? How are you dividing up the work?

In my experience, even with a very large complex mixed signal design, there is one guy per board, and in the extremely rare case that a single board is being worked by more than one person it is usually divided up by discipline typically, RF, analog and digital and those people contribute their pages in any number of ways including using sub-circuit modules out of an Altium library.

And, EEs lean heavily on reference designs and eval hardware to do their work. Though they do spend a lot of time reading a lot of data sheets they really don’t have time to read most of them, just reference the ones they need to integrate existing designs and handle the new parts of the design (which need to be minimal). They need to get large parts of the working designs handed to them with eval hardware they can test and vet on the bench, and with reference designs (schematics, layout, firmware and some documentation) provided by and supported, somewhat, by the vendors of the major components. Not some open source developers who can’t really support the major components utilized in their designs effectively because they don’t have access to all the information they would need to do that, talk to the fab etc. They can only talk to FAEs, same as all other engineers outside the vendor.

Also, PCBA design is very process oriented. Even if a company doesn’t have a PCBA design process this will not slow down an experienced EE who I say has learned what I call “The process” with a capital T. Schematic capture and layout are 2 very hard and fast steps in that process with boundaries that been defined by decades of EE college curriculum and EDA development that aren’t likely to see any change in EE in the near future, though I think the EDA industry is in need of some disruption somewhere, it is not here.

I started designing CPLDs and FPGAs right as most people had switched from capturing their chip designs in schematic form to capturing them in verilog and VHDL. It was a disaster. Most EEs in that space (including myself for a time) were really bad at architecting their modules and then structuring and writing the HDL code to make sense and be maintainable. Good documentation and block diagrams were essential for development and maintenance. And, after 20 years, it is still a huge problem for a lot of designs. I really wish someone would make a good tool to aid in the construction of block diagrams from the code of large FPGA designs. Too often I would inherit a legacy design and find myself having to spend a week or two creating block diagrams and other documentation for the design.

I shutter to think what it would be like to try to understand and debug a PCBA for a 20 layer board that was just a bunch of code or text and didn’t have a schematic and some decent documentation. It’s bad enough that EE’s are frequently handed a large schematic and layout with little or no documentation for it except a folder full of the data sheets for each component.

This article is certainly making the rounds.

I tried to google the title in firefox focus as I sometimes do to get around the paywall and found a weird youtube video of someone sleepily reading the article:

https://m.youtube.com/watch?v=w0wF_nne164

Lots of syndication in the serp also.

I like this one by “Lazy Boy”

https://youtu.be/9vGwDUcBHbk

Same, Sudafed is a silver bullet for me. The 12 hour release absolutely works to clear my sinuses and relieves the sinus pressure headache (almost completely when combined with ibuprofen).

My wife insists Phenylephrine works for her and thats all she will take. She has offered it to me a couple times when we didn’t have any Sudafed and Phenylephrine had 0 noticeable effects for me.

Edit: I forgot to add that Alavert-D 12 also has Pseudoephedrine and works for me too and is what I take when my congestion is allergy related.

Hey, guys. Looks like I am late to the show with my comment here, but I am pushing 20 years in FPGA dev experience and hoping that maybe I can share some perspective on what seems to be a reoccurring theme on HN:

Why aren’t there any open FPGAs or at least more Open FPGA tools? Why are vendor FPGA tools so huge, terrible and hard to use? Open FPGA tools are better and the way to go! etc.

In one of Dr. Cutress’ questions he states and then asks: > … they're just hard to develop for. You need to know how to use them before you use them , which sounds like the wrong way to learn how to code! What exactly is Lattice doing to kind of ease that transition for people who may understand software, but are kind of new to the hardware?

Why is this? What can Lattice do?

It’s because one does not “code” an FPGA, they design a microchip and that process involves a lot more than writing code. It is pretty hard to do right. FPGA is on the spectrum of VLSI microchip implementation technologies. That’s why they compare FPGA’s to ASICs in the interview.

Don’t believe me? Look at this article: https://www.tutorialspoint.com/vlsi_design/vlsi_design_fpga_...

So in general the progression is FPGA -> GA (Gate Array) -> Standard Cell ASIC -> Full Custom ASIC

FPGA development is microchip development. It requires a great deal of tacit knowledge, experience and a background in electrical engineering and digital design and a number of other skills to do well.

In order to develop open tools for these devices most of the devs in the community would have to have a lot of this knowledge and experience and most if not all of the FPGA vendor’s IP on all of their devices in order to work on an open tool chain. In the end an open tool chain will do little to alleviate all the pains of the chip design process anyway so it really isn’t worth the effort to make open tools. It is way easier to just use the vendor’s tools once you know what you are doing. Most of the tools have gotten much better in the last 20 years.

That is why you will not see open tools for anything but the smallest and simplest devices that can be reverse engineered.

IMO, the best thing lattice can do for someone who doesn’t have any experience with the technology is to point them to the Lattice Partners program to find an expert to help.

I am probably not making any friends here by saying this, but I welcome any counterpoints we might argue together here.

Not off the top of my head. I would definitely recommend trying to find a mentor with current experience rather than getting started by yourself if possible depending on your background. The last time I mentored someone and looked at beginner resources was over 10 years ago and at that time I was recommending beginners with at least some of the requisite college coursework buy and read "The Design Warriors Guide to FPGAs" to get started and then buy and use at least one of Peter J. Ashenden VHDL and Verilog texts as HDL language references. Much of The Design Warriors Guide might still be relevant but I haven't looked at in a while. Ashenden's books are probably still mostly relevant for the versions of the languages they covered, but these days I would try to also find a good book on SystemVerilog. All that is probably overkill towards the goal of learning more about computer architecture and the way CPUs work on a lower level though. For me I found all my undergraduate and graduate coursework, including a class on operating systems, to be essential to my understanding and real world use.

FPGA designer here. Just wanted to point out that “efficiency” is highly context sensitive in FPGA design. Everything is an area / speed / power trade-off. If you only need a ram that is 8-bits wide and 64 words deep then it might be way inefficient to waste a dedicated 18kbit block ram on it when it would fit better into 2 LUTs. This is why Xilinx, for one, provides pragma such as RAM_STYLE to help guide synthesis:

(* ram_style = "distributed" *) reg [data_size-1:0] myram [2**addr_size-1:0];

block: Instructs the tool to infer RAMB type components.

distributed: Instructs the tool to infer the LUT RAMs.

registers: Instructs the tool to infer registers instead of RAMs.

ultra: Instructs the tool to use the UltraScale+TM URAM primitives.

See: https://www.xilinx.com/support/documentation/sw_manuals/xili...

edit: formatting*

FPGA Pro here. I checked out the README.md to see if I could pick up any tips. It is a good guide for a first time through, but I recommend also reviewing the Xilix documentation on this.

There's Xilinx App Note 1165 [Circa 2013] which is getting long in the tooth but still valid: https://www.xilinx.com/support/documentation/application_not...

And, Chapter 5 in Xilinx User Guide 892 is "Source Management and Revision Control Recommendations" https://www.xilinx.com/support/documentation/sw_manuals/xili...

There is also a .gitignore example which can be helpful but is not geared towards a minimal file set without alot of tweaking: https://www.xilinx.com/support/answers/61232.html

A few words of warning here: The documentation recommends using the write_project_tcl and write_bd_tcl scripts. I have experienced problems with both of these not faithfully recreating the .xpr and .bd files so exercise caution with them. A better approach is to avoid .xpr files and to use a non-project or scripted flow. If you have to use a Vivado project for some reason (I can think of a couple) then create and maintain tcl script to generate the project by hand. One can use the write_project_tcl to get started and then update it by copying the tcl generated by Vivado after each GUI operation out of the Vivado tcl console into the project generation script when making changes to the project one wants to keep.

I have had the most problems with write_bd_tcl so I am now experimenting with just checking in the .bd file and setting the .bd extension to "binary" and various merge strategies in the .gitattributes file after several projects worth of frustration with the write_xx_tcl nonsense.

Finally, take all other Xilinx recommendation of source files to check in with a grain of salt. The documentation recommends checking in way too much. I recommend sticking with the "Minimum Set of Source Files to Manage" with archival backups of all output products for critical tags (eg. releases) somewhere outside the VCS.