sschmitt

Pretty good! Translation by AI? First lessons quite well, but first quiz in German "Welche dieser Noten ist... ganze Tonoberhalb?" makes no sense.

Can it document modular synthesizer patch configurations?

How is this different from https://github.com/nextjournal/clerk?

https://polioeradication.org/about-polio/history-of-polio/

What's the best strategy for a full backup and recovery if updating to LTSC goes wrong?

How has this changed with the successful implementation of LLMs in the recent past?

Cool! Will be interesting to compare to https://github.com/mit-pdos/xv6-riscv!

Shameless plug for my html version of the xv6 book: https://xv6-guide.github.io/xv6-riscv-book/

HTML conversion

https://xv6-guide.github.io/xv6-riscv-book/

and cmake build

https://github.com/xv6-guide/xv6-riscv/blob/cmake/CMakeLists...

for xv6: a simple, Unix-like teaching operating system.

There's also the BrainScaleS neuromorphic system that features wafer scale integration:

https://arxiv.org/abs/2303.12359

Jeffrey Snover, inventor of PowerShell, wrote in 2007:

"It was a mistake to think that GUIs ever would, could, or even should, eliminate CLIs."

16 years later. Has the situation changed? Will it ever change?

...commissioning of the first-generation BrainScaleS wafer-scale neuromorphic system

Jack J. Dongarra: "[...] somethings wrong with our architecture".

Neuromorphic systems open up opportunities to enlarge the explorative space for computational research. However, it is often challenging to unite efficiency and usability. This work presents the software aspects of this endeavor for the BrainScaleS-2 system, a hybrid accelerated neuromorphic hardware architecture based on physical modeling. We introduce key aspects of the BrainScaleS-2 Operating System: experiment workflow, API layering, software design, and platform operation. We present use cases to discuss and derive requirements for the software and showcase the implementation. The focus lies on novel system and software features such as multi-compartmental neurons, fast re-configuration for hardware-in-the-loop training, applications for the embedded processors, the non-spiking operation mode, interactive platform access, and sustainable hardware/software co-development. Finally, we discuss further developments in terms of hardware scale-up, system usability, and efficiency.

Also see the "Heidelberg Spiking Datasets": https://ieee-dataport.org/open-access/heidelberg-spiking-dat...