rsaxvc

No rush - been busy over here too.

Thank you for this.

Also small world, floating point JPEG person here.

looks like they never went 64 bit

My pet peeve is that grub repartitions windows disks on chain load, so if it ever boots with the disks remapped, there's a chance it'll plow apart the partition table of whatever poor disk got mapped to that hd#.

Long enough ago I don't remember the business details.

The 4.x compiler line never being patched was a bit of eye opener into commercial toolchain support.

I was still learning assembly, it took me a while to be sure it wasn't my bug.

You're eactly right. I saw the blight at Herculaneum, MO in the 2000s - dozers plowing down houses in a slowly expanding circle centered on the smelter.

1 in 5 students had excess blood lead. The schools nearby were scraped down and soil was replaced whenever the lead levels got too high from the dust blowing off the open ore and slag trucks running town. The smelter didn't hit EPA requirements for 25 years, and when faced with enforcement, decided to leave rather than produce lead cleanly, because it is not economical to do so cleanly. Cheap lead offloads the environmental and health effects to someone.

https://health.mo.gov/living/environment/hazsubstancesites/p...

https://www.kbia.org/science-and-technology/2012-08-08/the-e...

You could review their argument: https://www.ftc.gov/system/files/ftc_gov/pdf/YardiSOI-filed%...

Search for "adherence to the agreed-upon Prices", "fix list price", and "Express delegation".

They argue that collusion through delegation counts as price fixing. They argue colluding to set list prices even when there isn't a price floor is price fixing. They argue that replacing the delegation with an algorithm is still price fixing. Most of their arguments are based on already settled cases.

One might ask the same of us who use our initials on hacker news.

MIPS on GCC defaulted to trapping integer overflows, but they had non trapping instructions too.

Takes many bit flips to go from one pattern to another.

This happens near loads of broadcast AM stations.

https://www.reddit.com/r/audio/comments/rfmfkq/home_audio_sp...

I'd guess insurance companies. Who used to get it from oil change places.

https://abc7news.com/car-insurance-auto-mileage-odometer/133...

That's more the scale I was thinking .You'd still need a rechargeable battery or large cap to run the ESP32 in any useful mode.

I've been on one. Aircraft carrier.

Edit: commenter seems to be editing without noting their edits. This comment was written against a their comment in a different revision.

100 microwatts - I can't imagine a phone idles on that. About 36 microamps at 3.6 volts.

less than a coin at 15 x 15 x 5mm

Slightly smaller than a stack of four US dimes.

You can use a Windows build on wine.

Agreed.

Where it mattered for me was on an ARM core managing a much larger DSP. The DSP consumed most of the memory bandwidth, so fetching a cacheline of instructions or an MMU mapping into the ARM had long and variable latency as it had to wait for the DSP to finish a large burst to or from the shared memory.

Rarely if ever. This isn't about tail-calling, it's about function placement in the final image to enable branch elimination. There's no call between foo and foo0, but many of the requirements for a tail call are also required here

You can structure the code so foo calls foo0, but the compiler and linker have to work together to pull that off and I don't think GCC and clang do so.

If the functions are being built into split sections, generally no.

If they aren't, and foo isn't called nd foo is, I've never seen a tool chain remove just foo but not foo0, which is nice to have.

Ask your hometown to build an antigravity skating rink with magnet shoes.

It is not typical for contemporary GPUs or ICs.

Use island! It implements the MDM functions with an app you manage!

Another GPU friendly approach is mixing with blue noise. I used it in a display driver with XRGB8888 framebuffer and Y2 pixels, and it worked great.

Well, 20mm x 20mm, now I'm wondering about the 80...

Excel. Conditionally format based on constrain violations and difference from target baudrate. Brute force and scroll.

This reminds me of guessing codepoint likelihood based on character distribution.

It was, in the old days, 16-bit, IIRC.

Have faith in 8020.

Now please sell me RP1 chips!

This was excellent debugging and a great write up.

If the SHAREABLE bit is like on ARM, it won't effect a system running only one core. On some systems this causes memory ordering to that shareable IO memory to be ordered across multiple cores where it might not be otherwise. There's a performance trade off in that additional cache coherency traffic can be a bottleneck, but for something like a UART shouldn't be an issue and could be left shareable.