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random_duck

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Once again, I used Cocotb as the abstracting layer allowing me to interface with multiple different simulators. Namely, icarus verilog for my standard verification and CVC for the post implementation timing annotated netlist.

So you want to sprinkle the faster cell groups around, but the ecofiller gates are more flexible since they are everywhere by default ?

Normally you tell the fab to keep a few wafers after the base layers and don't manufacture the metal layers.

Oh, I had no idea that was a thing.

Oh thanks, this is really interesting. Is there a limit to how far you can scale down your node to build the full frame image sensor: is 180nm the largest feasible node?

The blank areas of the chips are filled with filler cells but most of them are special "ECOFILLER" cells that are basically generic pairs of N/P transistors like a gate array. These can then be turned into any kind of cell just by using metal. They are a little slower but work fine.

Oh, this is fascinating.

How to tell us you have a thing for sound generators, without telling us you have a thing for sound generators. Cool list !