petrohi

I remember using Soviet-made VAX clone from СМ ЭВМ series:

https://en.m.wikipedia.org/wiki/SM_EVM

I want to mention another awesome project, which implements PDP-11 on FPGA and can be used with PiDP-11 panel. (PiDP-11 by default uses software emulator running on Raspberry Pi.)

https://pdp2011.sytse.net/wordpress/

Not the parent poster, but my experience may be relevant.

My background is exclusively in software engineering and computer science. I started by reading “Digital Design and Computer Architecture”. There’s new RISC-V edition https://a.co/d/imzGBK5 as well as freely available ARM edition https://dl.acm.org/doi/book/10.5555/2815529. The book starts from Boolean logic and transistor technology and goes all the way to assembly programming with everything in between. Most importantly gives great introduction to HDLs. Next I played with a bunch of hardware projects specifically targeting inexpensive Arty-A7 board to get comfortable with FPGA tooling.

I can attest to the parent saying that this is sufficiently different from software engineering I do at my day job and therefore feels a lot more like hobby. Especially if you also foray into wire-wrap prototyping, PCB design and assembly. Finding and fixing analog "bugs" is so much fun!

I started by reading “Digital Design and Computer Architecture”. There’s new RISC-V edition https://a.co/d/imzGBK5. The book starts from Boolean logic and transistor technology and goes all the way to assembly programming with everything in between. Most importantly gives great introduction to HDLs. Next I played with a bunch of hardware projects specifically targeting inexpensive Arty-A7 board to get comfortable with FPGA tooling.

It has TTL RGBI and composite NTSC outputs. The latter is actually very interesting in that it can produce 16-color images using color smearing effect on NTSC TV. Many games from the period used this to achieve more colorful graphics at the expense of dropping to 160x200 resolution. OP port of Wolf3d is also supporting this mode.

I am working on FPGA-based converter to be able to show RGBI and composite CGA on modern VGA screens.

Yes, specifically IBM PCjr-ish clone. Compared to IBM PC 5150 it has 2x slower access to the first 96K of RAM due to “integrated” nature of its non-standard take on CGA. But, the rest of RAM is actually faster than IBM PC because it is a modern retro computing extension card made with fast SRAM.

Tried it on 4.7MHz 8088. Looks great but too slow to enjoy the gameplay.

This two-part blog explains step by step how to build a robot starting from training the ML model, using FPGA for hardware acceleration, writing an embedded C program and finally assembling everything on the chassis.

We work on an open source tensor processing unit at https://tensil.ai. It is not RISC-V based since only a handful of very simple instructions is needed for expressing data flows typical in ML.

Something like the Alveo PCIe card has onboard HBM/DDR4 memory large enough for Tensil DRAM pools, so this would be similar to how GPU operates but could also reach to host memory via PICe if needed. Embedded applications with Zynq 7 and UltraScale+ have ARM processors on the same chip with FPGA and (usually) DDR as separate chips on one PCB. In this case, Tensil DRAM pools are just contiguous memory blocks in the memory shared with the CPU. We will be publishing documentation on the compiler design soon--stay tuned!

Great questions! With Tensil, all computations are performed on the FPGA. In addition to matrix multiplication Tensil supports SIMD instruction with various operations. The ML activations, average and maximum pooling, normalization, and image resizing use SIMD instruction. Some ML operations, such as padding, are achieved by changing the memory layout. Tensil uses DRAM0 and DRAM1 memory pools (usually in DDR memory) to interact with the host to read model inputs and weights and write outputs. It also uses these pools to offload intermediate results between layers and between tiles within a layer when FPGA does not have sufficient BRAM, which is common on lower-end devices. Tensil compiler takes care of finding the most efficient memory scheduling for given on-FPGA memory size.

It’s possible to form monochrome VGA signal with an SPI, which is commonly available in microcontrollers.

I did little write-up on how to do it efficiently (DMA etc) on PIC32: https://hackaday.io/project/173682-color-ascii-terminal/log/...

Very glad to see Rust on PIC32! This microcontroller is one of the very few that is still made in DIP package making it ideal for breadboardind and easy through-hole soldering, and by far most powerful, making it ideal choice for interesting projects.

Hello HN. SIDfi is a single-board self-contained SID file player. SIDfi requires the original MOS 6581 chip or a pin-compatible replacement such as ARMSID. SIDfi plays tune files such as High Voltage SID Collection from a FAT-formatted memory card and displays current tune information on a small LCD screen. Buttons on the LCD screen can be used to control the playback.

SIDfi is still very much work in progress. I am planning to add ability to play specific SID tunes and directories with joystick buttons and improving playback screen presentation.

Have you tried MikroTik gear?

This is great! Would be also interesting to have side-by-side history of US, Russian and French nuclear power programs.

Shoreline.io | Redwood City, CA and REMOTE | Software Engineer (Distributed Systems) https://app.trinethire.com/companies/22646-shoreline-softwar...

Shoreline was founded to reduce operational pain. We have experience building and operating mission critical databases, cloud services with millions of hosts, and self tuning feedback control systems. We want to reduce tickets and improve availability by an order of magnitude through automation. We are well funded and based in Redwood City, California and Iasi, Romania.

Have you designed, built, and operated distributed systems? Love correctness, fault tolerance, and scalability? Shoreline is hiring distributed systems engineers to build our core product: a programmable & distributed control plane designed for scalability, fault tolerance, and portability.

What you'll be doing

- Implementing a distributed control plane in Elixir / Erlang and verifying, formally and through tests, to guarantee correctness and fault tolerance.

- Defining the semantics of the distributed ops language and implementing the distributed runtime.

- Designing & implementing a distributed event recognition and signalling system.

- Designing & implementing a distributed metrics subsystem and feedback control algorithms for distributed control.

- Build systems with arbitrary scale in mind e.g. millions of nodes. You'll use standard software development best practices such as version control and participate in software development processes such as code and design reviews.

We pay competitively. While this position can be remote, you may be asked from time to time to travel to and work from the main office located in Redwood City, CA.

Shoreline.io | Redwood City, CA and REMOTE | Software Engineer (Distributed Systems) https://app.trinethire.com/companies/22646-shoreline-softwar...

Shoreline was founded to reduce operational pain. We have experience building and operating mission critical databases, cloud services with millions of hosts, and self tuning feedback control systems. We want to reduce tickets and improve availability by an order of magnitude through automation. We are well funded and based in Redwood City, California and Iasi, Romania.

Have you designed, built, and operated distributed systems? Love correctness, fault tolerance, and scalability? Shoreline is hiring distributed systems engineers to build our core product: a programmable & distributed control plane designed for scalability, fault tolerance, and portability.

What you'll be doing

- Implementing a distributed control plane in Elixir / Erlang and verifying, formally and through tests, to guarantee correctness and fault tolerance.

- Defining the semantics of the distributed ops language and implementing the distributed runtime.

- Designing & implementing a distributed event recognition and signalling system.

- Designing & implementing a distributed metrics subsystem and feedback control algorithms for distributed control.

- Build systems with arbitrary scale in mind e.g. millions of nodes.

You'll use standard software development best practices such as version control and participate in software development processes such as code and design reviews.

We pay competitively. While this position can be remote, you may be asked from time to time to travel to and work from the main office located in Redwood City, CA.

Loïc Hoguin. The author of Cowboy web server. De facto standard web server in Erlang/Elixir. Foundation for Plug and Phoenix frameworks.

<shameless plug>

We at sameroom.io do this in sort of backend-only way.

</shameless plug>

It now has window._=function(d){ ... }

HE/Fremont IPs are routed to East Coast with 100% packet loss:

  3  te-0-3-0-3-sur03.santaclara.ca.sfba.comcast.net (68.85.190.45)  9.350 ms  10.003 ms  11.028 ms
  4  te-7-1-ur12.sanjose.ca.sfba.comcast.net (68.87.194.130)  12.359 ms
     te-1-1-0-7-ar01.sfsutro.ca.sfba.comcast.net (69.139.198.174)  16.199 ms
     te-1-1-0-9-ar01.sfsutro.ca.sfba.comcast.net (69.139.198.178)  11.900 ms
  5  te-0-2-0-0-cr01.chicago.il.ibone.comcast.net (68.86.91.121)  14.191 ms  16.276 ms  15.595 ms
  6  he-0-12-0-1-pe04.ashburn.va.ibone.comcast.net (68.86.87.2)  15.877 ms  15.729 ms  16.187 ms
  7  * * *

Great framework! Imho best at having powerful yet non-leaky and clear abstractions. We use it to build kato.im web app.

Erlang VM is built on the premise that it runs a functional language. I would argue that it will be extremely inefficient to implement non-function language to run on Erlang VM. By non-functional I mean language that is based on mutable and shared state. You can look at Elixir (http://elixir-lang.org/) to see great example of an alternative language that runs natively on Erlang VM. While offering syntax that is more familiar to many people Elixir retains all basic restrictions of Erlang.

Looking at Choice Criteria slide one might ask: why not Erlang?

Why Go over Erlang?

Great to see more adoption for Erlang/OTP. The return on investment is clearly there for us at connect.me. We're implementing our backend and API in Erlang/OTP.

Can you share what type of application you will be working on?

Great article. I've been inaccurate in the blog saying that cache coherence will or should go away. What I mean is that ugly (non-scalable) effects of cache coherence as implemented by today's vendors can be relieved by Erlang VM to some degree. In the comment above [1] I say "It can also scale well if sniffing is not a broadcast". Your article is to the point by addressing exactly this issue with tracking of sharers.

[1] http://news.ycombinator.com/item?id=4780706

Two most important differences that come to mind are 1) Erlang is dynamically typed language vs statically typed Haskell; 2) Haskell is functional language with lazy evaluation where side effects are the primary concern, Erlang has eager evaluation.

Erlang VM is much friendlier to garbage collection. For example immutability removes one of the biggest overheads of GC--tracking reference mutations. Process isolation allows to run garbage collection concurrently and without employing esoteric techniques. Many processes are short lived and never reach GC point, when they terminated memory is reclaimed wholesale.