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murderfs

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But what's the alternative for the trademarks that are truly universally known? Does it serve the public for me to be able to sell unauthorized Coca-Cola brand products, or more likely, the trademark owner selling a token item in each category to maintain the right to prevent others from using it?

Refunding is one possible remediation, see section 32 (cancellation) and section 26 (The consumer's rights in the event of defects). That option cancels the purchase contract, meaning you as the consumer give the item back, while the seller gives you the money you paid for the item.

Only if the manufacturer fails to fix it per section 31: "If the defect is not rectified and no redelivery takes place pursuant to sections 29 and 30"

I don't understand how this functions in practice: if business A sells a widget to reseller B who sells it to reseller C who sells it to the customer, there's multiple layers of markup. How can the original manufacturer be expected to refund the purchase price?

Reading the law, it does not say that the consumer is entitled to a refund.

The board game has extensive rules on mech design, but for weapons, it's just wherever they'll fit. Some of the built-in hardware has fixed locations: cockpit, life support, sensors go in the head; engines go in the center torso (with light and xtralight fusion engines spilling out into the side torsos as well), arm and hand actuators go in the arms, and hip, leg, and foot actuators go in the legs. You can see this in the critical slot section in a record sheet: https://i.redd.it/jt3p2f1v14gf1.jpeg

This one definitely deviates from tabletop: pretty much everything except the smallest weapons have an integral tonnage, and the weapons themselves don't line up directly with their tabletop versions.

The newer games tend to be absolutely consistent with the mech design rules in terms of what weapons are available, and their weights and sizes, such that board game designs are legal in the game (and usually the state you get the mechs in before you customize them), and customized mechs are legal board game designs. They tend to limit the customization by doing things like having mechs have predefined hardpoints that limit what types/sizes of guns can go where, because otherwise you just end up with every mech being identical, with maximum armor and the rest of the tonnage being spent on whatever happens to be the most optimal weapon.

I'll do better than a second case, here's three:

Barracuda Networks: https://krebsonsecurity.com/2013/01/backdoors-found-in-barra...

Fortinet: https://community.spiceworks.com/t/hard-coded-password-backd...

Korenix: https://sec-consult.com/vulnerability-lab/advisory/backdoor-...

The fact that the password is "rzadmin" makes it a lot more likely that this is just run of the mill stupidity, and not something more nefarious: you'd want a backdoor that isn't blindingly obvious and usable by the CIA.

They passed a tax on basically just Amazon in 2018 and there were rumblings of Amazon leaving the city for Bellevue/Redmond. The city council repealed it within a month and things quieted down, but then COVID happened, they passed basically the same tax again, and this time it stuck. Since then, Amazon's been slowly leaving Seattle for the eastside by moving employees as their building leases expire: https://www.seattletimes.com/business/amazon/amazon-no-longe...

I don't understand why people are so deluded about the value of metadata about them. It's not that valuable, you're not that important.

AOSP made it increasingly difficult to contribute without being an Android partner and it's nearly impossible now.

Yes, by "upstream", I mean "upstream Android".

Google didn't invent MTE or memory tagging.

Sure, they didn't invent memory tagging (SPARC ADI was an implementation from a decade ago, and I'd bet IBM had an implementation of something similar in like the 70s, judging by the rest of ISA innovations in the last decade), but they definitely invented the instantiation of it in ARM. Pretty much everything aside from instruction encoding for MTE was specified in a doc sent by Google to ARM in response to ARM telling Google something along the lines of "the entirety of our efforts in the security space are going to be spent on something that you're not going to see any benefit from within the next decade: CHERI aka Morello aka Arran".

They are "permitted" to access to Google Play Services because their work hardening Android currently benefits Google.

Very little in GrapheneOS has gone back upstream post-Copperhead.

Once Google feels like there is sufficient stability and compatibility with hardened memory allocator and tagged memory (and when they can get Qualcomm to support it across their range), they will make harder, until impossible, for Graphene.

What are you talking about? Google doesn't use hardened_malloc, and they literally invented MTE.

A 5090 gets you 32GB with 1.8 TB/s of memory bandwidth for ~$4k, RTX A6000 gets you 48GB at 768 GB/s for ~$3.5k, 2x 3090 gets you 48GB for $2000 or so, and if you're willing to go into the wilderness, there are much cheaper options like the AMD MI50.

So add it as an axiom with a comment pointing to the proof. If you don't trust the proof because you don't personally understand it, why are you using a proof assistant in the first place?

There are over 12,000 7/11s in the United States, and probably hundreds of thousands of competitors (certainly if you include gas station stores). The thing that's different about Japanese convenience stores is that, 24/7, they sell food that's incredibly high quality compared to what you can get in American convenience stores at extremely low prices, and that doesn't seem to be the case for Zabka?

When an invalid instruction exception occurs, it is very easy to identify whether the invalid instruction was an AVX-512 instruction, because those start with a prefix different from any other instructions.

You're missing the point: the processes executing AVX-512 do not have any particularly strong requirement for AVX-512 instructions, they're just optimistically using them to improve performance because CPUID claimed they were supported. It would be pathologically bad behavior to control scheduling behavior with this, because in practice it would result in things like glibc deciding to use AVX-512 for string functions resulting in every program that uses memcpy (i.e. every program) not being allowed to be scheduled on the little cores.

I don't think AI is particularly worse at multi-threading code than humans are: humans are notoriously bad at it. I've had reasonably good success with telling Claude and Gemini to go into a codebase, insert clang -Wthread-safety annotations, fix any issues it finds, and refactor code that isn't amenable to the annotations to make it possible.

The kernel can't do anything here, unless your answer is "threads can't ever migrate between types of cores, so cross your fingers on which core you spawn on". The kernel doesn't know what flavor of ISA userspace is expecting, because userspace doesn't know what flavor it wants until it actually gets to run: symbol multiversioning lets you compile a function for multiple versions of an instruction set and pick the best one at runtime.

You could imagine the kernel being clever and handling the first SIGILL in hardware and then marking the process as big-core-only, but you can't handle this generally since you can have new instructions get encoded as nop (I believe the AArch64 PAC instructions do that?). You could also have an ifunc resolver intentionally call the instruction and expect and handle the signal.

The solution is to make your hardware actually work, and not claim to support instructions that do not actually exist on all of your cores.

They didn't disable it at first on their client CPUs, and it resulted in code randomly crashing depending on whether ifunc resolvers first ran on a big core or a little core.

It's pretty surprising that multiple CPU vendors have run into issues like this (some more than once, fucking Samsung), when it's pretty much the first thing that anyone on the toolchain side of thing asks when they hear about heterogenous cores on a CPU.