joelby37

I've been experiencing exactly the same thing over a number of sites for the last few days too, with exactly the same user agent in this post. The annoying part is that it is not really 'spidering' web sites, but rather continuously hammering a list of non-existent pages which appear to be from a years-old version of the site.

Generating 404 responses puts a considerable load on WordPress sites and generates a lot of network traffic, but these have been relatively easy to block because of the predictable user agent and URI path prefixes. I'm thinking about blocking the Azure ASN completely, or developing something akin to Cloudflare's "are you a human?" interstitial page when requests come from cloud provider ASNs.

As an alternative, here's my list of cheap FPGA development boards: https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards . It covers a bunch of other vendors.

I totally agree.. I like the idea of YAML and source control for pipelines, but unless you're already very familiar with the system it is much slower. Fortunately there's a "Use the classic editor to create a pipeline without YAML" option to use the previous system.

The two pin plug that attaches directly to the power brick isn’t grounded, but the power adapter extension lead is and it solves this problem. https://www.apple.com/nz/shop/product/MK122X/A/power-adapter...

Thanks for the hot tip! I've been struggling with my monitor's menu buttons, but after reading your comment I found the macOS tool MonitorControl, which works perfectly.

From personal experience (other workplaces may have different policies), I can see why people in Japan would not change jobs very often. A large proportion of your salary can be in the form of performance bonuses, which you technically aren't eligible for when you first start. This means that you can take a huge pay cut for the first 12 months because you might only receive a token bonus.

Excellent point about the LEDs and switches - and that's exactly what I use then for! You can never have too many LEDs when you want to track the progress of a ponderous and misbehaving state machine. I'll update the article with a clarification in the morning!

A few years back I was working on a PhD project that involved software defined radio for tracking wildlife in real time, which was an ideal FPGA project. With a limited budget I was keen to find the cheapest boards out there, and decided to start maintaining the list.

Sadly I don't have much time to use them from day to day any more, but still help people out when they email.

The comparison of development environments is a great idea which I'll definitely work on! They have a baffling range of paid editions with different featured and it's difficult to know what they all mean and why you'd want them. Thanks for the idea :)

Using double-edge clocking usually comes from a misunderstanding about how FPGA timing works. When you look at a waveform in a simulator, it's intuitive to think that you would need to change states at opposite edges to guarantee setup time. The synthesis tools will actually guarantee that setup times are met even if you use the same clock edge, though.

Also, the use of a clock divider in this way is bad practice and another trap for beginners. Use clock that are on global clock lines, and use a clock enable to slow things down.

I concur - a few months ago I used the mobile Web site on an iPhone. I was idly scrolling around the "People You May Know" list while distracted. I noticed that if you merely scrolled the page by swiping and your finger happened to start on top of someone's profile, it would immediately invite that person to connect without any confirmation.

It was a pretty horrifying realisation that I'd become one of those random inviters - now I have much more sympathy to people I've never heard of inviting me to connect! I refuse to use the mobile site again, so I haven't checked if it's been fixed.

You're right - including 'D' in the sensitivity list is incorrect and is a good way to lead to the synthesis of latches. Sensitivity lists should only include the clock, or clock and an asynchronous reset, or if it's combinatorial logic, all signals (with no clock).

The best explanation I've seen for two and three process FSMs is that older synthesis tools weren't smart enough to infer an FSM from anything else. At least with FPGAs, it seems like the professionals are only using the single process model. Why wouldn't you? It doesn't separate related pieces of code over multiple pages and the chance for stuffing it up is reduced significantly.

Teach people to use the single process model. Teach them that two and three process FSMs exist so that they can identify and understand them, but don't waste too much time on it. Some of the textbooks I've read devote a chapter to the distinction between Mealy and Moore state machines. Time to let this one die!