jecel

The simplest processors use one clock per instruction with a Harvard architecture. This allows their control unit to be a combinational circuit instead of a Finite State Machine (and depending on how your memories work you might even avoid having an instruction register).

Most one-instruction processors take multiple clocks and often need extra registers (for fetching 16 bit addresses from an 8 bit wide memory, for example) [1].

The four instruction MCPU [2] is not as bad to program as the one-instruction computers (it still needs 10 times as many instructions as a RISC-V, for example) while being very simple. Making it Harvard allows it to be slightly simpler and making it 16 bits allows it to run non trivial programs [3].

[1] https://github.com/jeceljr/SBN/blob/master/sbn.pdf

[2] https://github.com/cpldcpu/MCPU

[3] https://github.com/jeceljr/digitalCPUzoo/tree/main/MCPU

I think there were actually 68000 transistor positions. In the ROMs and PLAs not every potential transistor is populated but the missing ones were counted as well. But the number of actual transistors is only slightly smaller so it doesn't really matter.

One chip that could be used as a memory mapper for the 9900 (but wasn't in the TI99/4A) was the 74LS670, which was used in the IBM 5150 PC to allow the 8237 DMA chip to access more than 64KB (a limit that wasn't a problem when used in a 8080 system).

Note that RISC5 [1], a project created as a target for Wirth's Oberon compilers, is a different project from RISC-V [2], a project created at Berkeley which became what is currently the most popular open source ISA.

[1] https://riskfive.com/RISC5_overview.htm

[2] https://riscv.org/

It is funny that RISC-V International moved to Switzerland in 2020 so now both projects can be found in the same place.

We were stuck with 33MHz PCBs for a long time as people kept trying and failing to get 50MHz PCBs to work. Then Intel came out with the 486DX2 which allowed you to run a 50MHz processor with an external 25MHz bus (so a 25MHz PCB) and we started moving forward again, though we did eventually get PCBs to go much faster as well.

The Transputers (mentioned in other comments) had already decoupled the core speed from the bus speed and Chuck Moore got a patent for doing this in his second Forth processor[1], which patent trolls later used to extract money from Intel and others (a little of which went to Chuck and allowed him to design a few more generations of Forth processors).

[1] https://en.wikipedia.org/wiki/Ignite_(microprocessor)

The naming of processor sizes is the subject of debate. I call a "pure 8 bit processor" one that has 8 bits for both data and addresses. Like the Kenbak-1. But these are so rare and educational rather than practical that it is very reasonable to call hybrid 8 bit / 16 bit processors just "8 bit".

This use of sloppy terms shouldn't make us forget that they are using an address extension trick, just like all those 16 bit processors that wanted to go beyond 64KB (for byte addressed such as the PDP-11, Z8000 or 8086) or 128KB (for word addressed, like the Xerox Alto's modified Data General Nova model).

Michael J. Flynn, best known in the computing world for his taxonomy of parallel computing (SISD, SIMD, MISD and MIMD), passed away on December 24, 2025

Two years after this booklet, the CRT memory it describes was replaced by core memory (becoming the first computer to use that technology).

Most people are not aware that after the failure of the PS/2 attempt to control the PC market, IBM tried a third time using 7 patents it had for the PC AT (they didn't have any on the original PC or the XT). In the first half of the 1990s they went after the chipset makers (mostly in Japan at that time) and in the second half of the 1990s they went after the PC makers themselves all around the world. The would threaten to sue for all machines made up to that point unless they licensed not only the 7 AT patents (which would expire in 2001) but also a bunch of other unrelated patents that were much newer. As far as I know everybody signed the deal, which meant that IBM could make money without actually making any PCs themselves.

Here is a one hour talk Stewart gave at the 2016 VCF East (Vintage Computer Festival):

https://www.youtube.com/watch?v=Ncnje4DdRxE

He mentions that the first year it was a live program and they didn't have the resources to record them, so they are not available.

QNX was my operating system from 1985 to 1988. I also studied it in 2000 for a project that ended up getting cancelled.

Initially the actual implementation didn't match the conceptual framework, but by version 1.2 they had really cleaned things up.

One issue he mentioned is still true today in Brazil's universities: while in theory you can ask to transfer from one course to another, in practice you have to drop out of your current school and take the entrance exam for the other one. And then you waste a lot of time trying to get your grades for the courses you have already taken recognized as equivalent so you don't have to start from scratch.

For him to move from math to electrical engineering to physics in Brazil would mean going through this twice. This might make him take some 7 or 8 years to graduate.

I guess this inflexibility makes things easier for the administrators. They know they will have 25 students in the statistics class in 2028 and so know how many teachers to hire to handle that.

Actually, the 68000 had one full (all operations) 16 bit ALU and two more simple (add/subtract, so AU might be a better name) 16 bit ALUs so in the best case it could crunch 48 bits per clock cycle. The 8086 had one full 16 bit ALU and one simple 16 bit ALU (the ancestor of todays AGUs - address generator units).

The 68000 actually had both microcode and nanocode, so it was even further from hardwired control logic than the 8086. In terms of performance the 68000 was slightly faster than the 286 and way faster than the 8088 (I never used an 8086 machine).

They should say on this page that this project has ended. There are some spinoffs people interested in this can look into:

https://tinytapeout.com/

https://wafer.space/

https://chipfoundry.io/

The Indy 500 was actually part of the official Formula 1 calendar from 1950 to 1960, though the two series diverged after that.

Some Indy features (refueling, changing tires even if they didn't have a puncture, safety cars) got adopted by F1 through the 1980s, specially as F1 started to lose audience to the American series in the early 1990s.

Though a problem, as you point out, it still happened. The 6800 based SWTPC was followed by 6809 machines what need to have all their software reassembled.

On the other side of the cpu wars, all those 8080 machines moving on the Z80s got to keep all their binary software, which happened again for IBM PCs and clones as those evolved.

https://en.wikipedia.org/wiki/SWTPC_6800

Thank you for correcting me. I don't know where I heard the story I mentioned.

My own memory of the events (which might be very wrong) was that a new vice-president of IBM semiconductors decided to drop bulk CMOS and focus exclusively on SOI (Silicon On Insulator). That suddenly left Transmeta without chips to sell. They had to scramble to find a new supplier and design their next generation processor for it (since the Crusoe wasn't portable to any other fabs). They were able to launch their Efficeon on TSMC 130nm (with a later version on Fujitsu 90nm) but the gap in supply was far worse for a startup than it would have been for a big company.

The VM in Slang had been previously published as part of the "blue book" (now that is what I call open source!) some 14 years before, and as the paper you linked to mentioned, Mario Wolczko at the University of Manchester had typed it in so it was available in machine readable form.

They did drop the object memory part completely and designed a new one from scratch.

Previously people had manually translated the VM from Slang to Pascal or C (I did so myself in 1986) but for this project they wrote a tool for that (in Smalltalk, of course).

Here is another copy of the "Back to the Future" paper:

http://www.mirandabanda.org/files/Papers/BttF.html

If we label the combinations of the seen and scanned bits as:

00: white

10: gray

11: black

then we cam describe it as a very cool variation of the tri-color gc algorithm.

https://en.wikipedia.org/wiki/Tracing_garbage_collection#Tri...

Finally, a programing job that AI won't be able to replace.

Well, at the recent VCF (vintage computer festival) Midwest they showed a robot using the Altair's front panel to toggle in a game:

https://techav.net/post/796938975198707712

Exactly, but the text has the same instruction sequence twice and the parent correctly indicated that the first copy should have used "lui" to illustrate the problem you mentioned and the second copy does use "auipc" to illustrate the fix you mentioned.

The problem with Self in the 1990s wasn't the lack of sources (I just checked the 1994 Self 4.0 sources and the license looks like the typical BSD one) but the fact that the binaries only ran on Sparc workstations and not the computers people actually had. I might as well post the whole text of the license:

# Sun-$Revision: 21.2 $

Copyright 1995 Sun Microsystems, Inc. and Stanford University.

All Rights Reserved. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in subparagraph (c) (1) (ii) of the Rights in Technical Data and Computer Software Clause at DFARS 252.227-7013 (Oct. 1988) and FAR 52.227-19(c) (June 1987).

Sun Microsystems, Inc. 2550 Garcia Avenue Mountain View, CA 94043 USA

LICENSE:

You may use the software internally, modify it, make copies and distribute the software to third parties, including redistribution for profit, provided each copy of the software you make contains the copyright notice set forth above, the disclaimer below, and the authorship attribution below.

DISCLAIMER:

Sun Microsystems, Inc. makes no representations about the suitability of this software for any purpose. It is provided to you "AS IS", without express or implied warranties of any kind. Sun Microsystems, Inc. disclaims all implied warranties of merchantability, fitness for a particular purpose and non-infringement of third party rights. Sun Microsystems, Inc.'s liability for claims relating to the software shall be limited to the amount, if any of the fees paid by you for the software. In no event will Sun Microsystems, Inc. be liable for any special, indirect, incidental, consequential or punitive damages in connection with or arising out of this license (including loss of profits, use, data, or other economic advantage), however it arises, whether for breach of warranty or in tort, even if Sun Microsystems, Inc. has been advised of the possibility of such damage.

AUTHORSHIP:

This software has been derived from the Self system, which resulted from the combined efforts of:

Bay-Wei Chang, Craig Chambers, David Ungar, Elgin Lee, John Maloney, Lars Bak, Mario Wolczko, Ole Agesen, Ole Lehrmann Madsen, Randall B. Smith, and Urs Hoelzle.

The early microcomputer market had three kinds of companies:

- those with organic growth, where the sales of products financed the development of new products: MITS, IMSAI, Sphere, Ohio Scientific, SWTPC, Cromemco, Processor Technology, etc

- those that were part of a larger company: Radio Shack, Commodore, Texas Instruments and Atari-Warner

- those that were financed by venture capital: Apple

In retrospect, the companies in the first group were doomed to not become an Apple. Later on we got many more venture capital based computer companies, with Compaq among the most famous.

In the case of Sphere it had many more problems than just how it was financed. They got an early reputation for not delivering at all or shipping non working products.

What was special about Sphere was that from a technical point of view it was a generation ahead of the competition: with a built-in screen it was more like a Commodore Pet or a Radio Shack TRS-80 from 1977 than like the boxes with LEDs and toggle switches from its peers in 1975.

You are correct about the US in relation to trademarks. The situation there is rather complex, with it being possible for people to just add TM to their texts and ask other people to do the same and it is considered legally binding. They can take the extra step of registering and then they add (R) to their texts and that gets them an even stronger legal case.

Because of the case law nature of the US legal system and the informality of TM, if other people start using the term in other ways (for example using "xerox" as a verb meaning "copy") and you don't show an effort to curb that then you can lose your trademark.

In other countries things are different. Brazil, for example, uses a Latin legal system which is more formal. So the only thing that matters is whether you have registered the trademark with INPI (National Institute for Intellectual Property) or not. Which is why Gradiente owned the iPhone trademark in Brazil even though they were not using it anymore (it was from a product from around 2000) and if you asked anybody on the streets in Brazil they would associate the name with Apple.

They hesitated a bit on continuing to release it as open source when they moved from Stanford to Sun (I should actually say Sun's lawyers hesitated) but then went ahead and released Self 2.0 sources (Self 1.0 and 1.1 had been open source). This continued with Self 3.0 and Self 4.0 and then the project was cancelled the first time as Sun decided to focus exclusively on Java. David Ungar was able to continue making small changes but neither the sources nor the binaries were released to the public.

Around 2000 Sun decided to restart the Self project with a embedded Self-in-Self called Klein and released Dave's improvements (including the PowerPC Mac port) while an outside group had done a port to x86 Linux.

I think it was 2006 when Sun cancelled the project again and Dave moved to IBM research.

So all the sources have been available since 1990, but with the delay I mentioned in the case of Self 4.1

They are completely different designs, but the name is inspired by the same source: the Mill component in Charles Babbage's Analytical Engine.

Very good points. About ARM1, 2 and 3, if my memory from 4 decades ago is correct then the changes from 1 to 2 were a move to a slightly newer process node, replacement of "multiply step" with actual multiply instructions and the addition of the co-processor interface. 2 and 3 are the same processor, but with the latter adding a 4KB onboard unified cache, which allowed it to run at a much higher clock frequency.

Thanks for the link. As Ken points out at the end, "Probably the biggest objection to calling the ARM1 microcoded is that the designers of the ARM chip didn't consider it that way.[4] Furber mentions that some commercial RISC processors use microcode, but doesn't apply that term to the ARM1". My opinion is the same as Steve Furber's, though I can certainly see Ken Sherriff's viewpoint.

In theory PLAs and ROMs are fully equivalent. In practice, while the ROM can accept any possible "microcode", a PLA might have to be enlarged if you want to change some of the "micro instruction". This need to change the hardware to change the functionality of an instruction is what makes me consider this design hardwired instead of microcoded.

[EDIT] Another issue is that the ARM1 has three pipeline stages. The "microcode" here is not used for the fetch and decode stages, only the execute one. So though register to register operations take 3 clock cycles to execute, only one "micro instruction" is needed (the second line in the table).