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It is really puzzling how a GPU could work in such latency constrained environment like RU. On the cost side - RU are built with on chip SRAM as a processing memory for cost,latency and power reasons, which is completely opposite of how GPU is built.
VLIW works great when you have predictable & short latencies of memory accesses - you will not find DSP designs that do not use TCM (core local SRAM). So you program DMAs input data into its own TCM and work on it from there. GPUs on the other hand hide latencies of memory accesses by switching threads when stalled
TI C2000 is one example
Cadence DSPs have C++17 compatible compiler and will be c++20 soon, new CEVA cores also (both are are clang based). TI C7x is still C++14 (C6000 is ancient core, yet still got c++14 support as you mentioned). AFIR Cadence ASIP generator will give you C++17 toolchain and c++20 is on roadmap, but not 100% sure.
But for those devices you use limited subset of language features and you would be better of not linking c++ stdlib and even c stdlib at all (so junior developers don't have space for doing stupid things ;))
Most of VRAN sites will be still DRAN (distributed RAN -server on site). CRAN (centralized RAN) is a fairy tale so far and works very few scenarios like very dense urban. Still we are talking about 200/400G NICs being standard.
L1 interface is also more efficient than it was for previous G’s where BTS sent time domain data, modern FH sends only allocated parts of spectrum in frequency domain.
The most amusing part is that Huawei developed 5G tech on its own - nokia has shit and e/// is not better. Even in regards of 4G massive MIMO tech - Huawei is years ahead of other, they couldn't steal this tech from anyone - because one one had it.
Huawei is far ahead of others in mMIMO technology and have this implemented in their BTS boards, although right now it is done in FPGA not ASIC.
I had to register to comment about TI "quality" and friendliness ;-).
Their SoCs are ridden with HW bugs and TI will not put every HW bug to errata - e.g. their infrastructure pktdma will hang if you will use chained descriptors but you will not find it in silicon errata. TI response was - "just don't use it" and refused to verify it on their side.
The ISA of c66x DSP is just stupid - you have quad SP multiply but only double SP addition - forming registers back and forth in quads will result in MV instructions often (because compiler is not so smart). There are no real vector registers, "vector" instructions take 4 or 2 32bit registers.
Want to compute power of individual complex int16 in a vector ? You are out of luck - DDOTP4H will add everything together.
There is even no way to utilize their multipliers fully since load&store is 2x64 bit, while multiplier can perform 8 SP multiplies per cycle.
Moreover memory access to L2 is so slow that you will wait in memory stalls (there is no HW prefetch from L2 to L1D cache) and L1 SRAM is way to small to do anything serious (32 kB).
After trying other DSPs, like CevaXC or VSPA, TI looks like poor joke. Their C7000 that supposed to address some of those problems is long overdue and will be well underpowered comparing to recent Ceva DSPs or NXP VSPA.