bit-hack

Thanks for the suggestion, I've added this license to the project.

The main reason is just due to me knowing my own limitations. SRAM is really simple to interface with and i've not yet tried to write a DRAM controller since its much more complex. Putting SRAM on the board made me more confident about the project. I did have it in mind that I could try to use the DRAM in place of the SRAM at a later stage (as you suggest) as a good way to focus on learning how to use it.

Thats an oversight on my part, I should put a license on it. I would love for anyone to be able to build one or tinker with the code as they want to. After all I was only able to make this because others shared their projects that I could learn from.

The bus controller was fairly straight forward. I found the timing diagrams in the V20 datasheet to be pretty easy to follow. The clock for the CPU is generated by the FPGA which I derived from a clock running at twice the speed, that made it easy to pick which clock edges I wanted to sample from or assert data for the CPU on. I did have a bug or two in there early on which meant that memory writes would not store the data I was expecting as I sampled the data bus at the wrong time. That was a tricky one as the bug would only become visible when that location was loaded from again. The CPU i'm using is rated for 16Mhz, but i've only tried to push it up to 10Mhz so far so I have a bit of margin. Some more issues might pop up if I push the speed higher I suspect. Its very stable as it is now and i've not seen any issues I could attribute to the bus handling.

a busy loop waiting for an interrupt to fire?

Oh fantastic! this makes me super happy to hear :) I'd love to play with it.

You mention that you have traced out every transistor from die photos, and I was wondering how much work there would be to make a netlist for the 8086 like that which was used to produce the visual 6502 simulator?

It that feasable or is there lots of work to do to get to that stage?

I'm loving your series on the 8086 btw :)

What I'm curious about is how this has been done. I don't think that the source for UT99 has been released, so does icculus have access to the source and has then ported it to emscripten, or has it been decompiled from x86 and then recompiled for WASM, or is it running on an x86 emulation layer programmed in WASM? I presume it was from source, given that everything else is prohibitively hard just for a demo like this.

This is great, I've been wanting an ISA card with an FPGA on it for a long time so that I can experiment. I've ordered a few of these PCBs to build some myself. Its very kind of the author to give the design away for free. I also really like the Lattice FPGAs for their FOSS tool-chain, which is a breeze to work with.

I've honestly never seen .C used in the wild. I imagine anyone whose written a bit of portable code would immediately realize this is a bad idea.

Its still blows my mind that he fit this in ~1k LUTs. I'm new to FPGA but the closest I got was about 4.5K LUTs for a comparable core.

I wish there were more easy to access material about timing and size optimization for FPGA.