artemonster

"We did not choose a MUD because it is charming. We chose it because its constraints make behavior measurable." I so fucking hate these LLMisms

bookmarked. will never open again

where are docs

A lot of my peers were adamant that nirvanas song is „smeells like team spirit“ because this is how pirated mp3 on local DC (i think it was called that) p2p exchange was called

This is not reddit, people actually read and understand sarcasm (most of the time)

Its not them. Its you. You are real, this is what matters. /claude

We are selfreplicating bots - can eat anything, self healing minor damage, very agile, autonomous. When we stop growing numbers the harvest will begin

Call us/ we won't pick up

love the humor

bash bashing i can understand. whats wrong with ts tho?

How so?

Gamers are notoriously bad at doing something like this. If next 6090 card comes with a shovel of shit you have to eat to get the card - most will do it, in addition to paying $5000

and just read these awful comments defending this nonsense and shifting the blame. so much arrogance its nauseating

still useless. I had an idea to offload parts of my game core into wasm leaving only UI in the browser - I abandoned that idea when there was absolutely zero possibility for me to debug in browser what is wrong with my core. i just rewrote everything to TS (from rust)

how can you? its running wasm in a browser, how do you see original C/Rust code and or variables

for me its undebuggability.

-"hey, look at our C Rust FORTRAN to WASM translator, blahblah"

-"uhm, cool, how do I debug it?"

-"yeah...about that...you cant!"

Is there alternative discovery algo? I dont want to be suggested same things, I want to see something new

I wish there was an option to render "executable" lectures as PDF too. Id love to scroll these while commuting to-from work

I asked Claude what he thinks about this blog post and was surprised by the level of self awareness (you cant call it like that but I dont have better word)

RTL is not code

>Of course it is.

most programming languages have that one serious key property that Ive mentioned above - ABSTRACTION. you can well reason about a function that calls another function addTheseTwoStranegObjectsTogether(arg, arg2) and make totally valid assumptions on how and what would happen. "executing" that code is a depth first call graph walk, pretty linear one too. You cannot do these things by reading RTL code, the state space is enormous, there is no "unusual machine" that executes it (if you mean simulators, thats a different thing). also you cannot reason even about simplest instances since they are stateful and that is in no way is exposed via interface connections

AI is advancing so quickly though, I bet it will be pretty good in a few years.

Time will tell :) Cheers

The very first sentence: "Large language models (LLMs) have shown promise in register-transfer level (RTL) design automation" I want to see some serious proof for this shitty claim. While LLMs excel at slop webapp codegen because the code is usually highly modular, composable and easy to reason about), LLMs understanding of RTL is just pure dogshit. A simple signaling protocol, even well documented with some temporal behaviour and even some ready made assertions that are picked up by formal verification tools for static proving - none of this helps any top tier LLM to grok whats happening. state explosion, temporal dependencies, no composition - RTL is not code, its construction for complex machinery and LLM suck balls at it. and all of this will not go away if you slop into existence some low quality DSL for netlists

Good catch! You want me to rewrite the paragraph to sound less like an LLM? (sigh)

this resonates with my experience. once every 3 years I try linux as primary OS for my home PC, I do small stuff with C/python, browse web and play factorio. I use linux in VM on my job daily, so I am not a beginner, but gosh, linux sucks. Everything breaks constantly even when doing NOTHING. Nothing ever works installing first try, you always end up googling stupid error message and stumble upon 250 other idiots that try to solve same issue. after trying 5 solutions, one (or combo) will hopefully work. Then, you can hang-up entire system by a stupid python script or your own buggy program and I miss unkillable always working task manager that can recover almost every hanger (and just stfu about reisub) without needing to restart the whole system and killing my FKIN FLOW! ugh. I just use WSL2 for rare cases where I need my unix build tools and forever abandoned the idea of switching to linux. Life is too short wasting it on googling some nonsense shit that just have to fucking work.

Is there any research in composing state machines?

All fine, where is pelican on bicycle?

I am always puzzled by such articles - its actually very well made, drawings are good, little interactive pipeline animations are fine. But in order to follow it you must already know and understand what its writeen about and if you dont - the content is just noise for you.

nah, something like LLMs wouldnt be possible due to sheer power consumption - abstract (FL)OPs/uW is billions worse than modern tech. I used claude to make me back of a napkin calcs - single LLM prompt in 6502 era tech would be over 3k Eur vs fraction of a cent today, DISRECARDING WALL TIME (which is ridiculously impractical)

Imagine in steampunk fashion wed get an alternative future timeline where computer tech froze in 80s due to some physical limitation that prohibited shrinking transistors. all typical laptops would have same config as this awesome project. what would the society become?

Ofc blocking assign is used too and even it that always_comb case scheduler splits eval/assign into 2 phases!

dont know if trolling. SR latch you can do with 2 NANDs, or NORs there are plenty of *digital* circuits with that functionality, and yes, there are very rare cases when you construct this out of logic and not use a library cell for this. pulse circuit is AND(not(not(not(a))),a) also rarely used but used nonetheless. to properly model/simulate them you would need delta cycles

Please stop bickering about verilog vs vhdl - if you use NBAs the scheduler works exactly the same in modern day simulators. There is no crown jewel in vhdl anymore. Also type system is annoying. Its just in your way, not helping at all.