adapteva

Does anyone have the backstory on this?

Exactly why we zero asic is making Platypus devices open bitstream and all tooling foss from day one...to protect the world against future evil/dumb version of ourselves.

https://www.zeroasic.com/platypus https://www.zeroasic.com/projects/wildebeest https://www.zeroasic.com/projects/logik

Of course we don't have silicon yet...so nobody here cares. I think a lot of people forget that Xilinx spent $10B+ develop their awesome devices. I figure we can do it with 1/10th of that.;-)

Thank you, comment made my day:-)

Yeah, this was a big dilemman You can't compare two different compilers for two different hw targets. That would be like benchmarking GCC compiling to ARM with LLVM compiling to x86.

Thierry's synthesis scripts are really very clever, and the go way beyond our Platypus FPGA arch. We are realistic that until we have seilicon nobody cares about our arch. Releasing the work as open source, we think someone should adapt the code for all of the other targes I Yosys (xilinx, lattice...etc) so that everyone can benefit.

We contribute a lot of code to open source, but as an FPGA vendor we are not going to spend time/money optimizing compilers for our competitors:-)

Documentation can be found in two places. What else do you need to know?

https://github.com/siliconcompiler/logiklib/tree/main/logikl...

https://github.com/zeroasiccorp/wildebeest/tree/main/archite...

I am sorry you that's how it looks...can't argue with feelings, We did everything we could to give credit. Open source SW should be a stack and every project needs a proper name as a reference. I do find the statement a bit ironic though, b/c 99% of Yosys users don't know that 99% of the logic synthesis sauce in Yosys is done by ABC.

https://github.com/zeroasiccorp/wildebeest

No strings common share purchase means cash in hand, which implies Intel can spend it on any operational cost, including buying billions in TSMC wafers (which they already do).

Any strings attached? If not, ironically a big chunk of those US tax payer dollars will likely end up in Taiwan/TSMC.

Weird title, makes it seem like a reveleation. There have been numerous Viking treasures discovered in Sweden with traces from the the Islamic world and it's well known that they were all over England as well.

https://en.wikipedia.org/wiki/Spillings_Hoard

The only novelty claimed here is transparency. Binary compatibility is possible by documenting the complete architecture and the sequence of bit stream loading. It only refers to devices in the same architecture (eg z1000).

We'll see whether binary compatibility is a big deal to folks. Some would argue that you can always recompile the source code. There are applications where that is not an option...

First off, this is an eFPGA core not a chip. It's intended for folks who want to build their own ASICs with a small amount of embedded FPGA logic.

The LUT is a boring text book 4-LUT. Fancier versions are in the works. The point of the first standard is to be the lowest common denominator of FPGAs that anyone can implement, else the threshold is too high. Kind of like RV32I.

Oh no, we have lost another giant! Very few people in the world know the gratitude she is owed. I doubt Nvidia and the other fabless companies would exist without her contribution. I met her through DARPA in 2018 [ref] and I later reached out for advice when I started a company in 2020. She was kind and generous with her time in all of our interactions. Beyond her technical prowess, she really understood people. The community/collabroation aprpach she used to launch the VLSI revolution in the 1970's are worth studying.

RIP

[ref] https://youtu.be/W_cB8VYunY8?si=9M9QVmBipbKUXxMR&t=1414

Yup, got an cold email from them. Marked it as spam and never heard from them again...

Yes, that's a great idea, but none of the projects you mentioned are ready for production. Who will find the building of these products?

Yes

Makefiles can work for simple builds. Logik being Python based can do so much more: automated metrics gathering, conditional flows, parallel execution, error handling, dependency management

Haha, cool to see this on HN.:-)

Yosys and vpr is clearly doing the heavy lifting here...the novelty here is the fact that an FPGA startup is giving public access to the fpga pre production and is opening the bit stream format. This hasn't really been done before.

Absolute statements are bad.

Ten years too early....

https://parallella.org/2015/05/25/how-the-do-i-program-the-p...

There is no guarantee that it will, but...

case #1. If you truly have something custom IP, we could save time/effort by only chipletizing that part rather than working on the while SoC. The design and verification is an exponential function with respect to complexity(#blocks, die size). We can turn RTL into a 2mm x 2mm brick fairly easily.It would require a fab shuttle/mask sets though.

case #2. Depends on huw much power goes to the PL vs other functions. For PL dominated FPGAs that you fill up to the brim, our only value would be to help like in case #1. For multi chip solutions (FPGA + CPU) with small amounts of PL, a corretly designed small catalog of off the shelf chiplet approach wins.

The swappable nature of the chiplet bricks was meant to convey that they are the equivalent of toy plastic blocks. We didn't disclose the standard yet, this will be coming soon.

The RISC-V chiplet a standard RV64GC. The high level spec is at: https://www.zeroasic.com/docs/cpu

No my bad for not being clear. If all you want is a bunch of LUTs then the high end fpga is the right answer. FPGA today is a lot of other things besides PL (serdes, cpu, DSP, ML, DDR IF...) and some of those features are only available on the bigger FPGAs. FPGA portfolios have man gaps due to the enormous costs of designing each one of those FPGA products.

Thanks for the feedback. The access mechanism will be adjusted going forward. This was my bad.

Each chiplet comes with its own tool chain. The FPGA has a full RTL2BITS tool chain, the CPU is supported by standard RISC-V tools, and the ML chiplet will have a typical ML programming flow. The full system parallel heterogeneous programming challenge is something the whole industry is grappling with. It's an unsolved problem. DARPA started a program on this topic in 2020 called PAPPA.

The manycore emulation demo kind of hints at where we are going...more information to follow in the next few months.

https://www.zeroasic.com/emulation

Depending on who you ask, the silicon area overhead of programmable logic FPGA is 25X-100X compared to hard coded logic of an ASIC (at the same node). Very few applications can afford the cost of full platform programmability with large devices costing over $5K.

https://www.digikey.com/en/products/detail/amd/XCVM1802-1MSE...

If a catalog low performance $1 mirocontroller is good enough, then it's probably the right answer. A low cost FPGA (~$5) with an embedded CPU is also a great choice.

If none of the off the shelf components can meet the application cost, power, performance, size, weight, security constraints, you have the choice of either abandoning the project or spending $10M-100M to design an ASIC. Our chiplet approach fills the gap between ASICs and off the shelf FPGAs.

Do folks prefer FB?

No relation. Zero ASIC predates Matt Venn's "Zero To ASIC" course. We made some announcments on Twitter and LI in 2020 to announce company formation, but Matt didn't see them. I agree that the name collision is unfortunate.

ASICs are very diverse with many dimensions and it depends on the definition. Pure ASICs like bitcoin miners are very rare. Most "ASICs" are generally on the programmable platform spectrum (apple socs, snapdragon, versal, ML startup chips, Nvidia, amd versal,...). Take a look at the Apple SoC or Versal Soc of heterogeneous archs with a bunch of different programmable elements integrated.

Also...there is way too much emphasis on compute, most applications are IO/ memory bound. How many memory/serdes channels, total I/O BW, on chip cache sises, what type of I/O is much more important than peak theoretical flops/w.

Thank you!