VitaSetLLC

Edit:

It's not like they called you a slur. Just because two States are fighting doesn't mean that a Ukrainian civilian living in Ukraine has to beat up a Russian civilian living in Ukraine because they can't pronounce a Ukrainian word.

I am also Ukrainian, but I do not want my ethnicity to be known for petty violence.

Also I have applied to ask them to add my project to their NGI Fediversity Fund. Here's what I entered:

1. Proposal Description:

  The Vita FPGA Architecture Subproject is licensed under The VitaSet License.

  The VitaSet License is a permissive license which does not offer any implied warranties and patent grants and does not require the inclusion of this license's text on binary and hardware forms of the source code that is licensed under this license.

  This is to prevent executables and computer chips from wasting resources on including license text, but for source code to keep copyright attribution, so that when source code access gets interrupted, no claim of copyright infringement can be made towards the developers, as the claimant would have the copyright header of this license.

  The Vita FPGA Architecture Verilog files VitaFPGAArchLogicBlock.v and VitaFPGAArchMemoryBlock.v are bugfree.

  Any Vita FPGA Architecture Logic Block can act as though it is an Vita FPGA Architecture Interconnect Block. Thus, any possible truth-table can be expressed with enough Vita FPGA Architecture Logic Blocks, Vita FPGA Architecture Interconnect Blocks and Vita FPGA Architecture Memory Blocks. Thus, any integrated circuit could run on the Vita FPGA Architecture, given enough Vita FPGA Architecture Logic Blocks, Vita FPGA Architecture Interconnect Blocks and Vita FPGA Architecture Memory Blocks are available.

  Vita FPGA Architecture Chip and Toolchain Investment Proposition

  I am the Founder and CEO of VitaSet LLC.

  Over $400 have been donated by my relatives to me during late 2023. No other funds have been raised.

  https://github.com/efabless/clear - The Open Source FPGA ASIC. A open source Apache 2.0 eFPGA + VexRiscV CPU Chip that only sold a couple hundred physical computer chips before they stopped selling anymore through Tiny-Tapeout. I did not read their source code, my Vita FPGA Architecture was designed exclusively by me entirely from scratch. I have however read the GitHub Issues of the Clear FPGA Project and I see someone asking about the bugginess of the reset circuitry. My Vita FPGA Architecture is bug-free and permissively licensed under an open source license.

  Reducing the environmental waste caused by upgrading computer hardware, as simple software updates can be issued to update the FPGA Bitstreams instead of manufacturing new physical computer chips.

  Also, people can take advantage of the Vita FPGA Architecture to code up and use Hardware Accelerated Programs when computer chip transistors stop getting smaller.

  The Vita FPGA Architecture is synchronous clocked logic with an synchronous reset, so unlike the incompatibility of asynchronous integrated circuits, it will be compatible with the synchronous clocked ecosystem of commercial integrated circuits.

  https://github.com/VitaSetLLC/VitaSet-LLC-Asymmetric-Cryptographic-Public-Key

Unlike those commercial FPGA companies that haven't open sourced their FPGA Architecture source code, VitaSetLLC has, available on https://github.com/VitaSetLLC/VitaOS-Libre under a permissive open source license.

Also the Vita FPGA Architecture Logic and Memory Blocks are bug-free.

The Vita FPGA Architecture Verilog files VitaFPGAArchLogicBlock.v and VitaFPGAArchMemoryBlock.v are bugfree.

Using two input, one output nand or two input, one output nor gates, one can express any possible truth table.

The VitaFPGAArchMemoryBlock.v file implements a D-Flip Flop with two configurable inputs and two configurable outputs that output the same value in two directions.

The VitaFPGAArchLogicBlock.v file implements a LUT2 with two configurable inputs and two outputs outputting one bit in two directions.

A LUT2 can be programmed to ignore one or both inputs.

Thus, any possible truth table can be expressed with enough Vita FPGA Architecture Logic Blocks.