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Jaso1024

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lol, yeah, the time should be fixed though rn I think? depending on what level of difficulty you select in the racer game. The wiring is something I've been struggling with, working on making it better.

I intentionally made it s.t the truth tables are based on not just the input into the node, but based on all actual inputs to the node (so if you have additional processing on input x and y, itll show you the not w/ respect to input x and y and not just the immediate input).

will add a rotating cue in the next update

not to my knowledge, but i'd consider adding this in (i'm planning to extend to TPUs and apple silicon NPUs later, so i might just add this in aswell). what would one want the levels to look like?

Next update has warnings about bus contention (multiple things into one node) when its an issue, and will have a proper show solution button.

For level 1.1 the solution is basically to take the ground and use that as a singular input to the source pin of an nmos transistor, let the input to the level be the gate pin of that same nmos transistor, and to let the drain (top) pin of that nmos transistor connect to the level's output

oh its b/c of the contention between the outputs of the ands for the answer, u need an or gate to merge them (ill add an update w/ visual feedback for these sorts of thigns)

yeah, I felt that when playing myself, do u think this level is not necessary given previous levels? (it would also help me if u indicated ur level of familiarity w/ the concepts s.t i can calibrate)

good point, made an update that added difficulty levels to the minigames (handles the timer), and i'll probably move the truth tables minigame to after the user builds the truth tables, thx

Thanks for all the feedback! I've fixed some of these issues (e.g., capacitor levels, switching back to prior levels upon finishing / refreshing, deletion (theres a sign when you hover a component now)), but many of them i'll be fixing today.

I'll be uploading arcs 3 and 4 soon (which will be programming the CPU and the start of GPU arch soon (people have gone through arcs 1 and 2 slightly faster than I expected)

makes sense, idk if i want to remove times altogether (i personally found it fun + i want the game to be fun for all levels of familiarity), but ill add a modal to explicitly select difficulty level at the start of the racer game, i def agree w/ u overall

Oh, the drain should only be connected to the output, not drain aswell (irl this would kill one's chip, I'll add a feature to show short-circuiting). on pmos the source should be vdd, on nmos the source should be gnd (this doesn't apply for some later levels, but does for earlier ones).

Yeah, I had added it to make it compatible w/ my simulation system, just changed how I was handling the levels altogether, if it still has 3 try doing a hard refresh (Ctrl + Shift + R on windows, cmd + shift + R on macos)

lol, I hadn't seen that video before but its a good one. Na, this is the guide to comp arch that will (hopefully) end all instances of toil over documentation for any sort of processor when learning

Hi everyone, commenting to address feedback:

- Made timed minigames optional (e.g. binary tables)

- Added 7 (optional) intro levels to walk through pmos and nmos transistors

- Fixed the bug in the capacitor levels

- Changed editor bg to use dots instead of lines to fix wire confusion