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Brashman

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I spent a term at Cambridge in Electrical Engineering. Our tutorial sessions were very similar to recitations in America and classes still had traditional lectures. I'm not sure if this is different for other fields.

How are the results sorted? When I search "Spider-man", the first result is Boomerang, and none of the results on the first page are for the Peter Parker Spider-man (result #2 is Ben Reilly Spider-man).

I got to Challenge #5 by just having the elevators go to every floor like in the first example. It'd be nice to have an earlier challenge with only a single elevator force you to have a more complex controller. With 4 elevators going at a time, it's harder for me to "debug" and figure out how to use the API.

Ten seconds of math 12 years ago

Does it speed up or end eventually? I stored up 150 seconds left before I decided to quit (score of 2529).

Yes, too underwhelming to catch on as much as Gladwell's interpretation has. However, it actually makes an important point: even if you're talented, it requires practice to really become an expert.

I thought that the original study was just showing a correlation. That is, that experts typically had 10,000 hours of practice into their field of expertise. People have claimed causation since then (i.e., 10,000 hours guarantees expertise). The weaker claim that 10,000 hours of practice is necessary (but not sufficient) in order to become an expert seems reasonable to me.

On the other hand, I don't really see the need for stores to be unique. I go to stores to buy things. If they have what I need, that works for me. I think it's easy to associate big box stores with the ones that people tend to dislike, but there are also high quality places like Wegmans that are still big box, suburb-y stores.

It seems that much of the suburb vs. city debate comes down to culture and personal preference.

Lisp CPU 12 years ago

As written, that INIT section is really going to limit clock speed. I also don't understand why currentState is double clocked.

Lisp CPU 12 years ago

It sounds feasible, but I believe you would also have to augment data values in memory with this type. Every 32 bits in memory would also need a few bits associated with it for type and the memory buses would need to be widened to move these around.

The Joy of Typing 12 years ago

I was a college student during this time. I feel like people my age all ended up proficient at typing because of instant messenging (not just the "computer guys"). It was my preferred mode of communication of in high school (especially since this was pre-smartphone). I'm definitely surprised that they found typing speeds that slow.

Boosted is using Loaded longboards which are high-quality longboards. As a longboarder, it gives me confidence that the board will be fun to ride as opposed to being just a plank of wood on wheels. On the other hand, those Evolve boards look decent. The costs of all of these are really too high for me right now, so I'll admit I haven't seriously looked into it.

High level synthesis for C is not quite there yet to be used as a replacement for Verilog or VHDL, especially for high performance hardware. Verilog and VHDL are still commonly used for hardware design.

That might just be the weight that it can life from low to high height. It might be able to still support more than that when static. It would be good to know what it can support statically.

I think a big reason is the chicken-and-egg problem. GPUs gained large spread adoption because of their use for gaming. It's only relatively recently that they've been exploited for more general compute purposes. There hasn't really been a "killer app" for FPGAs that warrants many people to have one.

Take a look at VTR (formerly VPR): http://code.google.com/p/vtr-verilog-to-routing/. It's an academically developed tool for doing FPGA place and route. At the end of the day, you'll still need to use the proprietary tools to convert to the appropriate bitstream, but this an open source solution for the "heavy lifting" portion. However, last I checked the solutions produced by VPR aren't as good as the commercial tools.

From what I've seen and heard in the (academic) computer architecture community, performance and power gains often diminish when moving from theory to simulation to RTL and into silicon (It seems the Mill team is aware of this too). Thus, I tend to be skeptical about large performance/power gains. On the other hand, it's not entirely unreasonable that VLIW could see these gains. I'll be curious to see what happens with Mill. It seems to me the biggest challenges with VLIW architectures are on the compiler side and the need to recompile legacy code.