3JPLW

Is your home folder on a network drive?

That same format string is used in multiple places, and unfortunately I don't think the text engine they expose to us is smart enough to do the ordinal 1st 2nd 3rd thing.

Edit: oh, we can do that. Changed experimentally.

The problem is a minor placement issue for the `@simd` macro: https://github.com/kostya/benchmarks/pull/317

As an administrator at Julia's discourse, I'd be really curious if this was the reason. Discourse's default "short date" format is super problematic. By default, they display something from 5 days ago as `Mar 20` and something from a year ago as `Mar '20`. We've changed that to have the year+ old posts display as `Mar 2020`, but maybe we should also change the recent display to be something different; maybe `20 Mar`? The UI doesn't give us too much space, unfortunately.

The feature I'm most excited about is the parallel — and automatic — precompilation. Combined with the iterative latency improvements, Julia 1.6 has far fewer coffee breaks.

A thread from 2020 (v2 RC 1): https://news.ycombinator.com/item?id=22030928

2015: https://news.ycombinator.com/item?id=9315152

2014: https://news.ycombinator.com/item?id=7381877

2011: https://news.ycombinator.com/item?id=2784515

Benefits are highly regional. Where I live, the current latest sunrise is 8:06 am on December 5. I can't imagine a sunrise after 9am being very fun.

Yeah, you (used to?) be able to do multi-room audio with the original Airplay, but it was only supported from Macs. iOS did not support it.

Lots of the sciml.ai packages and documentation use Weave — you can look there for some examples. Here's one:

https://diffeq.sciml.ai/stable/tutorials/sde_example/

I encourage folks to actually read the linked article instead of basing their commentary on the shoddy title.

https://www.nature.com/articles/s41928-020-00523-3

Abstract:

Resistive memory technologies could be used to create intelligent systems that learn locally at the edge. However, current approaches typically use learning algorithms that cannot be reconciled with the intrinsic non-idealities of resistive memory, particularly cycle-to-cycle variability. Here, we report a machine learning scheme that exploits memristor variability to implement Markov chain Monte Carlo sampling in a fabricated array of 16,384 devices configured as a Bayesian machine learning model. We apply the approach experimentally to carry out malignant tissue recognition and heart arrhythmia detection tasks, and, using a calibrated simulator, address the cartpole reinforcement learning task. Our approach demonstrates robustness to device degradation at ten million endurance cycles, and, based on circuit and system-level simulations, the total energy required to train the models is estimated to be on the order of microjoules, which is notably lower than in complementary metal– oxide–semiconductor (CMOS)-based approaches.

No, it mostly affects execution time.

Citation needed. Yes, the -1 appears in the source code. It might even appear in the intermediate representation. It'll even show up in the assembly for multidimensional arrays (but it'll all get folded into a single `mov` assembly for vectors).

But I dare you to actually demonstrate a performance difference. Compared to a memory access, a `dec` is free.

Or how about just waiting until it gets merged and officially adopted?

From that study:

Limitations: ... no assessment of whether masks could decrease disease transmission from mask wearers to others.

This has always been the main motivation for mask wearing, but the study you cite didn't attempt to answer it.

Yeah, but this is a laptop chip at ~20W. Of course it's not going to compete with a 16-core 120W monster.

Getting 1/4 of the performance with 1/4 of the (high perf) cores and 1/6 of the power is very impressive.

Poor response, as pandemic safety 101 would prevent this:

- wash your hands

- wear a mask

- practice social distancing

- avoid extended periods indoors with non-household members

https://www.cdc.gov/coronavirus/2019-ncov/prevent-getting-si...

It's not just about protecting you, though. It's also about protecting our limited healthcare resources.

Every year I get the flu shot to protect me, you, and our shared healthcare.

I'm not "free" to ignore stop signs, stop lights, and speed limits. They impact my freedom to drive as I'd wish -- because otherwise I might hurt you.

I'm not "free" to start cooking commercially out of my home kitchen without inspections and licensing. This impacts my ability to earn an income -- because otherwise I might make you sick.

It's public health risk mitigation. We do it all the time.

This is a good resource for thinking around limiting transmission risks:

https://english.elpais.com/society/2020-10-28/a-room-a-bar-a...

This is why speed limits are prudent.

This is why masks and gathering limits are prudent.

Some of the NaN-handling issues are unique, but the compiler availability itself is still a problem.

https://twitter.com/StefanKarpinski/status/12929837172128931...

Since then, GCC has stepped up with this out-of-tree build, but it's still not 100% to my knowledge.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96168

Which is likely why there are some "7 core" GPU M1 chips.

Especially given this:

That 1948 study of 43 machines in Detroit showed ranges from 16 to 75 roentgens per minute. In 1946, the American Standards Association had issued a safety code for industrial use of X-rays, limiting exposure to 0.1 R per day.

I'd be curious how much a typical modern dental x-ray emits, but we no longer measure in roentgens these days as we have better measures of the actual dose (sieverts).

The proper shoe shouldn't reinforce bad running habits. If you got pushed that way by a one-on-one shoe fitting, you certainly did get "conned."

As someone who has had only one professional running shoe fitting in my life, I found it invaluable. They were able to immediately identify where my stride was going wrong. They advised me not just on the shoe, but on improving my gait. I bought one full-price shoe once, then was able to buy similar shoes on sale/clearance. Following the fitting (and guidance), I've not had the same knee pain since.

YMMV, but it's not all cons. It's a middle-ground between nothing and a full-fledged sports therapy.

BinaryBuilder/BinaryProvider are 100% functional and have been deployed and working for a long time now. The timeframes for individual packages to move to using them instead of ad-hoc build scripts, however, varies. It's generally very quick to do this, but complicated chains of binary dependencies can be a pain.

I wish they package a standalone Julia IDE

That's precisely what Julia Computing's JuliaPro is. https://juliacomputing.com/products/juliapro

(Full disclosure, I am employed by Julia Computing)

it's still shared

Right, that was really my main question: besides the labeling (which is of course approximate), the positioning sure looks like each core would have its own "favorite" section of the cache. And being shared, it seems like this could make for some interesting performance behaviors.

Ah, interesting, this topology was introduced with Sandy Bridge. I'm just out of date: https://www.anandtech.com/show/3922/intels-sandy-bridge-arch...

I'm talking about this image:

https://images.anandtech.com/doci/16063/474551355-Intel-Blue...

I don't see any coherent fabric blocks — what looks like large cache sections to my eyes are entirely inside the "Core" blocks. Maybe they're just not drawn correctly. Here are some much older i7s, for example:

https://www.cs.uaf.edu/2009/fall/cs441/proj1/russell/images/...

https://www.notebookcheck.net/fileadmin/_migrated/pics/Core_...

The chip image surprised me: where's the L3 cache? On previous generations, L3 cache was a significant amount of real estate. Is it no longer shared between cores?

Yes, that was this event.

Of course we were bound

Absolutely, the question was only how frequently it happens. The bet was within the first 100 detections — with one side only saying they're rarer than that.