Announcing PilMCU, the Lisp Machine on a Chip

http://www.mail-archive.com/picolisp@software-lab.de/msg04823.html

by jkleiser • 12 years ago

162 34 12 years ago

mail-archive.com

sbenitezb• 12 years ago

Do you have a diagram with the design? Something to amuse people even more? ;)

unwind• 12 years ago

It's a Verilog design for a new chip. But it doesn't seem to be open, at least I can't find the source anywhere.

It seems they're interested in launching this is a commercial (or crowd-funded) hardware product.

programmer_dude• 12 years ago

No links to the actual thing?

emeraldd2• 12 years ago

I wonder if this is related: http://picolisp.com/wiki/?home

daveloyall3• 12 years ago

That's PicoLisp, which you can apt-get install.

This is PilMCU, a hardware design which apparently runs PicoLisp.

Right now, only the design exists, not physical hardware. But you can run the design in a simulator. ...Something, something, verilog. (This is not my area of expertise.)

[Edit: the devs use the Icarus verilog compiler to provide simulations. It's available in Debian repositories.]

daveloyall3• 12 years ago

Here's more information about the actual thing...

http://www.mail-archive.com/picolisp@software-lab.de/msg0483...

...But still no links to source. (As I understand it, this hardware design is expressed in the form of verilog source code.)

emeraldd2• 12 years ago

I'd really like to see the full ISA, etc for the chip. A few years ago, I was doing research on building a byte code based vm after working through Peter Michaux "Scheme From Scratch" http://peter.michaux.ca/articles/scheme-from-scratch-introdu.... (I highly recommend running through his code, but do the GC earlier, it's easier to get it from the start than to try to add it.) I couldn't find anything online listing the kinds of instructions you'd want in a lisp chip.

pjmlp2• 12 years ago

There are a few PDFs with the original Lisp Machine ISA, if I am not mistaken.

I will have a look when back at home.

kjs3• 12 years ago

If you mean the LMI Lisp machine: http://bitsavers.trailing-edge.com/pdf/lmi/

There's significantly more for the TI Explorer Lisp machine: http://bitsavers.trailing-edge.com/pdf/ti/explorer/

And even more for Symbolics: http://bitsavers.trailing-edge.com/pdf/symbolics/

Xerox did a Lisp machine line: http://bitsavers.trailing-edge.com/pdf/xerox/interlisp/

There's a working emulator for the MIT CADR: http://www.unlambda.com/cadr/index.html

And you can of course run Genera in an emulator: http://www.unlambda.com/download/genera/

There's a semi working TI explorer emu: http://www.unlambda.com/lispm/

Symmetry2• 12 years ago

The original Lisp Machines were conventional machines with hardware features like tagged pointers that let them execute Lisp more quickly. I'm under the impression that the machine in the article is far more radical.

auvi• 12 years ago

there's something similar done before, Lisp machines in FPGA [0] [1].

[0] http://www.frank-buss.de/lispcpu/ [1] http://www.aviduratas.de/lisp/lispmfpga/

Symmetry2• 12 years ago

So this is something where the hardware is executing something that actually looks like LISP sort of like the Reduceron does with Haskell?

bd_at_rivenhill• 12 years ago

Is verilog design small enough to put on an FPGA?

tejon• 12 years ago

FPGAs are the only context in which I've ever encountered Verilog, so I'm gonna say yes?

DigitalJack• 12 years ago

Verilog is a hardware description language. You describe the hardware connections, sometimes with high level constructs like "for" loops, sometimes by just describing the gates themselves. In a sense, it is similar to HTML describing a web page, but with higher level constructs available like loops. So maybe HTML with a templating engine is a closer analogy.

For simulation, you compile verilog with a software tool into something executable by a VM or natively. This is heavily event based in execution, with events being edge transitions (a signal going from 0->1 or 1->0) occuring at specific times--for most (but not all) cases.

For producing something usable by an FPGA or a foundry for an ASIC, instead of compiling you synthesize. Different tool. Synthesis is the process of taking higher level hardware descriptions and outputing the lower level descriptions usually called a netlist. It's akin to translating C into assembly for example.

Device specific tools can take that netlist and create a bitstream for configuring an FPGA, or the foundry can take that netlist and go through a process called "physical synthesis" which takes the netlist and chooses from the foundry's library the components that will work best for that netlist to operate at speed, figure out where to place them on the die, and insert buffers as needed.

What the GP was asking: is this design small enough to fit in an FPGA. This question is orthogonal to the language used to describe the hardware.

I'd say they answer is yes, depending on the FPGA you choose. Some FPGAs are pretty high capacity these days, and even fast.

alain94040• 12 years ago

At some HN users' request, I started a Verilog guide for software engineers here: https://en.wikibooks.org/wiki/Programmable_Logic/Verilog_for...

Enjoy (improvements and comments welcome).

sklogic• 12 years ago

Your CPU (and likely >90% of the rest of your hardware) is designed in Verilog.

grondilu• 12 years ago

Talking about Lisp machines. I don't know much about these things but I was thinking about them recently when Hewlett Packard announced its so-called Machine^1. They want to build a new kind of OS for it, but wouldn't a Lisp machine just do?

[1] http://www8.hp.com/hpnext/posts/discover-day-two-future-now-...

rthomas6• 12 years ago

Where is the verilog source?

Pufe• 12 years ago

where's the kickstarter page? I want a few of those.

Flenser• 12 years ago

Can it run emacs?

daveloyall3• 12 years ago

I think emacs needs a POSIX-like environment to run inside. (I think this is roughly correct even though I don't really understand what it means.)

dozenal• 12 years ago

I've heard a few people suggest that with single core performance stagnating we may see more ASICs. I admit I'm skeptical, but this line of development does seem worth exploring.

Animats• 12 years ago

Yes, it can be done, but the half-dozen or so LISP machines of the 1980s were not very successful. Price/performance was worse than compiled LISP on common CPUs.

There's no indication of hardware support for garbage collection. It would probably be more useful to have tag bits to support GC than a LISP-oriented instruction set, especially if it allowed concurrent GC.

Announcing PilMCU, the Lisp Machine on a Chip

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