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Agiler: An adaptive heterogeneous tile-based many-core arch for RISC-V

https://ieeexplore.ieee.org/document/9759395

by rbanffy • 4 years ago

35 4 4 years ago

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ieeexplore.ieee.org

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4

TooSmugToFail• 4 years ago

Wonder what sort of computational tasks this architecture is particularly suitable for.

1024bees• 4 years ago

I appreciate the code snippets they put in the pub; when HW papers abstract that out, the system doesn't feel grounded in reality. Still, the open problem for this class of architecture IMO is programmability. A composable, well designed API for many core machines would be worth it's weight in gold.

btach• 4 years ago

Looking at the title and skimming the diagrams, vaguely reminds me of a souped-up TIS-100.

vardump• 4 years ago

Transputer lives! Would be a lot of fun to tinker with one of these.

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