Sunny Cove: Intel’s Lost Generation

https://chipsandcheese.com/2022/06/07/sunny-cove-intels-lost-generation/

by ingve • 4 years ago

130 24 4 years ago

rektide5• 4 years ago

This is going the be the first in a series of articles on CPU architectures. We’re picking up where Real World Tech left off with its microarchitecture deep dives. And we’re going to be doing them with the advantage of 20-20 hindsight, and hardware to test on.

I really miss this part of the cybergeekdom. Staring deeply at minor/major tweaks to architecture ("oh they switched from 4-way to 8-way associative cached!") was such a very real very physical very truthful part of computing for so long. We all got to see what was happening.

Today if you buy a Google laptop or phone, they won't tell you what generation or model cpu you are getting (Pixelbook Go's tech specs: "Intel m3"), what clocks it has. It's such a different age from where we were. It's so hard to believe that we can sell a laptop & have no idea what powers it. It makes sense, but it's still a system shock everytime to me.

mhh__4• 4 years ago

Most computers are still easy to work out CPU they have.

Especially the new Apple ones because they're so hot right now.

charles_kaw2• 4 years ago

The issue is not that it's easy to work out, the issue is that these manufacturers have decided that fine grained specs aren't important. I actually more or less agree with that, although I wish they'd at least indicate generation.

skavi• 4 years ago

The details are all out there. The Pixelbook’s m3 is an 8100Y. This uses Kaby Lake cores. There are plenty of details on Kaby Lake here: https://en.wikichip.org/wiki/intel/microarchitectures/kaby_l...

There were also plenty of details released on Google’s Tensor SoC in the recent Pixels. Of the top of my head, I know it uses two X1 cores and is manufactured on a Samsung process.

rektide5• 4 years ago

How did you/we find out it uses a 8100Y? What was the earliest date this was known? Was this knowable before the first devices started arriving at users doors?

ARM in general has been pretty opaque. This article shows so wonderfully precisely how many details we used to be in tune to. There's so many buffers, caches, lookups, &c. We used to be able to know it all: the cpu makers used to often tell us what the architecture was, so we could make pretty pictures like this. Comapratively, knowing something is a Cortex A53 will tell you some of this general picture, but I think a decent bit of it is configurable too.

Often we can go do the basic research, find out what chip a phone uses, go lookup L2 and L3 cache sizes, eventually (often after release, once people can test & find out). I don't know if any of these are knowable before devices start arriving, to be honest. I don't know how many more tuneable parameters a Cortex A53 has. Ex: can the caches have different associativities or are those fixed?

Since we've talked about Tensor some, it might be interesting to go review & compare this article versus what Anandtech (a pretty fine deep-tech site) has been able to unearth on Tensor[1]. It's not clear what all their sources are, but to be fair it's not immediately obvious what cheese & chips's sources were here. The article itself cites a code-drop that they seemingly mined to find a bunch of the specifics. But again, I just have no idea how many parameters are tuneable- we know already from above Cortex A53 <> Cortex A53, that at least cache size can vary, but no idea if cache configuration or parameters can vary. The article itself highlights that not only do they not understand the memory caching subsystem, for example, they don't even know if it's the same or different than the Exynos:

Google also integrated 8MB of system cache, and for me it isn’t exactly clear if this is the same IP Samsung uses on the Exynos 2100. Seemingly they’re both 8MB, but I’m leaning towards saying that it’s a different IP, or at the very least a different version of the IP, as there are some real differences in the way it’s architected and how it behaves.

I think of the Alex Russell tweets about Cortex A53[2], which can be anything from an awful forsaken terrible chip to an ok reasonable chip. Depending on how it's built up. Consumers generally just don't know much. Even the educated ones, in ARM land, have enormous fantastic limits of knowability: we take so much on faith. We can't assess what we are buying. ARM is opaque. Oh and it's also still sometimes selling us a 10 year old core (A53's decennial is October. Perhaps the upcoming A510 is "A5-10", a celebration of yet another decade of the same core? Frowny face.).

[1] https://www.anandtech.com/show/17032/tensor-soc-performance-...

[2] https://twitter.com/slightlylate/status/1180484877105483777

ip26• 4 years ago

As computing has matured, we have added layers of abstraction. All of what you describe is still there if you want it. Most people have moved to a different layer of abstraction, however.

Think of the people who grew up manipulating network data before the OSI model. They probably felt the same way when later 4 was abstracted away.

doctor_eval• 4 years ago

What are you talking about? I struggled with the move from DB25 to DB9.

yjftsjthsd-h• 4 years ago

I think some of it is that it really doesn't matter anymore. There was a time when every tweak mattered, when every little detail could impact the way the machine worked... but that's not true, for most people, anymore. Sure, they'll still call out the big things that might matter - this phone ships with our new super AI chip, this tablet adds extra low-power cores to prolong battery, this box has the latest video codecs in hardware - but really, you could take the CPU out of my last phone and drop it into my current phone and I wouldn't notice. Heck, if not for binary compatibility, you could take the CPU out of my last phone and drop it into my current laptop and I'd barely notice.

seoaeu• 4 years ago

Yeah, it is also a matter of the changes having a smaller impact. “Feature X improved performance by 1%” or “Removing feature Y cost 2% performance, but freed up the transistors for feature Z for a net 0.5% percent win” are the kind of changes we get these days

userbinator• 4 years ago

I think it makes sense only from the perspective of a company who wants to profit as much as possible off the ignorance of its users. They have a real incentive to obfuscate the truth and "abstract it away" (to use the politically-correct language) so they can then make changes and do things like this:

https://news.ycombinator.com/item?id=28314072

https://news.ycombinator.com/item?id=22906959

rawoke083600• 4 years ago

Agreed !

I've been trying to find out the "manufacturing nodes size ?"(like the nm size) for things like micro-controllers and "RAD Hardened CPUs" just cause it will be fun to compare, most of the docs/spec sheet I casually found doesn't mention any of this :/

scrlk• 4 years ago

Sadly over the last ~10 years, a lot of good tech journalists have left the space: Anand went to Apple; David Kanter no longer posts to RWT (though the forums remain a goldmine); Andrei Frumusanu and Ian Cutress left Anandtech - they are both consultants now.

Happy to see Chips and Cheese carry on the legacy!

fancyfredbot• 4 years ago

This is a fantastic piece of technical writing. Detailed and clear. Much better than my usual source for this kind of information. Going to have to read more from here!

Shtirlic• 4 years ago

Thank you, fantastic article, very interesting AVX part, btw: love my 1065g7 ;)

whinvik• 4 years ago

It feels like with the "demise" of AnandTech, cool articles like this have become rare.

Sunny Cove: Intel’s Lost Generation

Related Stories