SiFive to Debut RISC-V PC for Developers Based on Freedom U740 Next-Gen SoC

https://www.cnx-software.com/2020/09/15/sifive-to-debut-risc-v-pc-for-developers-based-on-freedom-u740-next-gen-soc/

by guerby • 6 years ago

170 59 6 years ago

cnx-software.com

guerby• 6 years ago

Press release:

https://www.businesswire.com/news/home/20200914005108/en/SiF...

jagger272• 6 years ago

Bring it on. If Arm is the future of desktop computing, it'll need a competitor.

klelatti• 6 years ago

Indeed, plus a viable competitor is the best way to ensure Nvidia is a reasonable steward of the Arm ecosystem.

mhh__6• 6 years ago

The likelihood of ARM sailing off into the distance and x86 disappearing is very slim. It's worth keeping in mind that they have more in common than you might think (i.e. RISC and CISC don't mean a huge amount any more when the old x86 instructions aren't used any more and ARM had/has a JavaScript instruction)

giancarlostoro• 6 years ago

So if RISC-V adopts WASM would that give it an interesting edge? I'm not a hardware guy, all software, but definitely would love to see a little more diversity in consumer grade hardware.

nsajko• 6 years ago

x86 has a quite variable instruction size, up to 15 bytes. So an x86 decoder will be more complicated than an ARM or RISC-V decoder. I'm pretty sure that means that designing performant IP is more difficult engineering-wise for x86.

aiilns• 6 years ago

Sorry for going off topic, but your comment confuses me. Doesn't "sail off into the distance" mean to disappear? But you're saying the opposite in your comment?

My reasonibg being that when a ship sails off into the distance it disappears from view.

brucehoult3• 6 years ago

"ARM has a Javascript instruction" is just misinformed.

They have always had the FCVTZS instruction which converts a floating point number to an integer (just as every instruction set has). If the floating point number is too large to fit in an integer then the bottom 32 bits are returned.

The new(ish) FJCVTZS does exactly the same operation except that if the floating point number it too large then the largest integer is always returned.

The implementation complexity difference is just about zero. It just so happens that the new instruction fits what JavaScript wants while the old one fits what C wants.

There is certainly nothing non-RISC about FJCVTZS. It's a perfectly simple instruction.

mhh__6• 6 years ago

Speaking of competition, I was reading the Mill news board and apparently they were planning on taking a step up this summer but COVID meant they couldn't do it. (But they are still ticking along)

pabs32• 6 years ago

Sadly the Mill is by no means an open ISA, mostly because of all the patents they are filing.

farseer• 6 years ago

Have not seen any RISC-V offering from the Chinese yet. I wonder if SiFive will have any competition.

krasin3• 6 years ago

Here you go: M5Stack tiny computer with a camera, LCD and RISC-V AI-capable Chinese chip (Kendryte K210). Available on Digikey for $26.50: https://www.digikey.com/products/en?keywords=K027&v=2221

FullyFunctional• 6 years ago

Please note that it has a non-working MMU and is limited to 8 MB of DRAM. This is not the SBC you were looking for.

m0zg• 6 years ago

This is not Linux-capable though. The choices are FreeRTOS and bare metal. The chip is pretty unbelievable at that price though. You get a lot of functionality for $9. And it works - I have it on my desk.

mhh__6• 6 years ago

Last time I looked at it (few months ago) the K210 had absolutely awful documentation (datasheet was basically just a pinout) in English and Chinese.

Not awful but for a high margin product I'd just use a US arm chip (e.g. LPCxx).

rwmj3• 6 years ago

AllWinner are doing a big run (50 million rumoured) of RISC-V chips through TSMC.

jagger272• 6 years ago

Do you have a source for this? I'd love to know what node they're using. I'm guessing no better than 12nm, but who knows?

GoOnThenDoTell• 6 years ago

Which company designed the riscv cores in the soc?

sitkack2• 6 years ago

Have you looked? Not seeing means you should probably turn on the light switch. You are in a dark room.

pabs32• 6 years ago

Sounds like Alibaba might be working on something:

https://www.nextplatform.com/2020/08/21/alibaba-on-the-bleed...

adrian_b• 6 years ago

Alibaba have presented their Xuantie910 RISC-V processor, one month ago at Hot Chips.

It is by far the RISC-V CPU with the highest performance ever designed.

Nevertheless, to reach that performance, they had to add a custom instruction set extension with indexed addressing modes, as a workaround for the greatest defect of the RISC-V ISA, its incomplete set of addressing modes.

etaioinshrdlu• 6 years ago

I wonder to what extent the digital logic design is open source. The RISC-V core ought to be, but what about the memory controller or PCIE root complex, (or USB3)? Those parts are also very important.

gchadwick• 6 years ago

Just because it's RISC-V doesn't mean it's open source. RISC-V is an open architecture so anyone can make an implementation but those implementations can be closed source. SiFive have released some open source stuff (https://github.com/sifive/freedom) but the majority of their work is closed source IP. In a way they're quite similar to arm.

userbinator• 6 years ago

Just like ARM, the only thing standard is the core and there is massive (and almost always publicly undocumented) diversity of everything else.

Taniwha• 6 years ago

There's not just one RISC-V core, one of the great things is that there are many, of varying complexity and performance. Some are very open source some are not.

There's already GCC and clang support, linux is here too.

gnufx3• 6 years ago

GCC doesn't have support for this system's vector unit in the development source as far as I can see. Does LLVM?

nickik2• 6 years ago

If this is anywhere reasonably price and has open firmware, I'm in.

ncmncm6• 6 years ago

Sigh. Still without the Bitmanip instructions.

Meaning, no popcount :-P

brandmeyer3• 6 years ago

That spec is just a draft, and still undergoing revision. Its close in spirit to a Scheme RFI (request for implementation). Until the consortium ratifies it (ie, members state their intention to implement it), its just a wishlist. A well-reasoned wishlist, but a wishlist just the same.

ncmncm6• 6 years ago

Exactly the point: no popcount.

It is just hard to imagine the thought process that would leave something as important as popcount to such a dodgy and long-delayed prospect; hard to imagine omitting it from the core instruction set, so that it is only ever implemented, if ever, in the most distended and expensive chips.

sitkack2• 6 years ago

It isn't as if RISC-V implementors are precluded from extending or implementing the bitmanip spec.

brucehoult3• 6 years ago

There are a number of companies asking that popcount not be included in the standard Bitmanip extension, but be optional, because it is expensive to implement.

ncmncm6• 6 years ago

Yet, far less expensive to implement than to code around the lack of.

This is all the more reason to get it into the core.

SiFive to Debut RISC-V PC for Developers Based on Freedom U740 Next-Gen SoC

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