Gathering Intel on Intel AVX-512 Transitions

https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html

by matt_d • 7 years ago

126 48 7 years ago

travisdowns.github.io

BeeOnRope15• 7 years ago

Author here, happy for any feedback or to answer any questions.

shaklee34• 7 years ago

No questions, but really enjoyed your blog, and your comments on this website over the past few years.

ksec• 7 years ago

Just want to say Thank You. Do you know anything about on AMD's side of things?

Note: For the really short version, you can skip to the summary, but then what will do you for the rest of the day?

Spending rest of the day on HN. /s

BeeOnRope15• 7 years ago

I don't know specifically, e.g. if there are any such pauses on Zen. Also, Zen doesn't yet support AVX-512 so a big possible source of variation is moot.

I don't know if any AMD chip has ever had different turbo speeds for any ISA. It should be noted that even without that, any chip can still run slower with heavier instructions because they hit some other limit: thermal, TDP, current, etc.

AMD has used an interesting "adaptive clocking" scheme since steamroller, and apparently this is still in effect in Zen:

https://www.realworldtech.com/steamroller-clocking/

This handles the same type of voltage droop worst case that Intel apparently handles by dispatch throttling. It would be interesting to test it, since the clock elongation should be visible when you measure instruction timing relative to a clock not affected by the adaptation.

oddity• 7 years ago

It’s a real shame avx-512 has so many eccentricities when it’s a much nicer ISA than anything before it (in x86 land). I would almost prefer a more predictable, high-latency decomposition into 4x128 wide uops over what we have now.

zwegner2• 7 years ago

But what about instructions like vpermi2b, which does 64 parallel 128 byte table lookups? The AVX shuffle instructions were hamstrung by the split into two 16-byte halves...

BeeOnRope15• 7 years ago

Yeah, the shuffles are awesome in AVX-512.

dman2• 7 years ago

Intel really botched the launch of AVX-512. By not making it available on client, and even on server having it be available on select chips meant that no one code coded / optimized for it. If you are proposing new instructions make sure they are widely available.

xscott3• 7 years ago

Additionally, it looks like each subset of AVX-512 past the foundation is an optional feature and needs to be tested for. With only a few exceptions (usually as a result of bickering between Intel and AMD), previous ISA extensions implied you had everything that came before it too.

In practice this means you could pick a few entire subsets: Legacy+SSE2 is always there for 64 bit, maybe test up to SSE4.2 for another subset. Maybe switch everything from REX to VEX if it has AVX and AVX2. That's effectively three back ends, which is manageable. With AVX-512, everything beyond AVX-512F is a la carte, and that adds unwanted complexity for instruction selection in a compiler.

Just look at all the separate AVX feature flags from CPUID:

https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_F...

Between the performance problems and complexity, I think it'll be a while until AVX-512 is attractive.

inetknght4• 7 years ago

As a developer who's micro-optimized some genetic software, I can confirm that I'd considered AVX-512 but decided against it after learning that the hardware being purchased by the company would not have the full AVX-512 feature set desired and it was simpler/easier to just write it in AVX2. Getting the software to also work on older/cheaper hardware made the business owner happy too.

BeeOnRope15• 7 years ago

If I could choose, I would like everything to run at the max turbo frequency all the time, yeah.

Still, and despite writing this post which will make a lot of people express something similar to what you wrote, I consider myself an AVX-512 fan, not the other way around. It's the most important ISA extension since, well, I'm not sure: a long time (probably AVX and AVX/2 combined would have a similar impact).

It introduces a whole ton of stuff that is very powerful: full-width shuffles down to byte granularity with awesome performance, masking of every operation, often free, compress and expand operations, and a longer list at [1]. That's only from an integer angle too (what I care about).

Yeah, it's taken AVX-512 a while to get traction (the fact that generation after generation of new chips have just been Skylake client derivatives with no AVX-512 hasn't helped), but I hope we are reaching a turning point.

These transitions are something you have to deal with if you want max performance, and I think we'll come up with better models for how to make the "global" decision of whether you should be using AVX-512.

---

[1] https://branchfree.org/2019/05/29/why-ice-lake-is-important-...

ComputerGuru• 7 years ago

The never-ending Skylake is/was a real problem. Intel was slowly adding features in a manner where it made sense to target last n generations but then all that came to a perpetual stop and suddenly we have this new extension that you can only really use on the very latest and most expensive, with virtually no backwards compatibility.

The instructions are sufficiently different from AVX2 that any appropriate use is not as simple as sticking it behind a gate and using a smaller block size, it basically requires a completely separate (re)write to properly take advantage of.

blattimwind• 7 years ago

It's the most important ISA extension since, well, I'm not sure: a long time (probably AVX and AVX/2 combined would have a similar impact).

IMHO the most important ISA extension since AMD64 was AES-NI, which moved a major consumer of CPU time into the also-rans.

chx• 7 years ago

it’s a much nicer ISA than anything before it (in x86 land).

It's coming from Intel Knights Landing. Previous massively multicore Intel offerings used a Pentium core and had a different 512 bit SIMD instruction set, KL used a Silvermont Atom core and introduced AVX-512 and parts of it were implemented in the Skylake Purley platform in a desperate attempt to give KL more software. With little to no actual adaption and the desperate situation of being stuck on 14nm and overselling those capabilities because they expected most CPUs to move over to 10nm it was no surprise the Knights... chips got the axe. But, the insanity of AVX-512 having an entire menu of possible instruction subsets stayed.

zwegner2• 7 years ago

Note that the 512-bit Larrabee instructions (on Knight's Ferry/Corner) had different encodings (and IIRC different encodings between KNF and KNC), but it was essentially the same instruction set. The few differences there were between LRBNI and AVX-512 had (AFAIK) almost nothing to do with the move from the old Pentium in-order core to Silvermont.

I think it's also safe to assume that, given the lead time to design an ISA and integrate it into an architecture (many years), the merging of AVX-512 into Skylake wasn't done "in a desperate attempt to give KL more software".

These slides from Tom Forsyth provide lots of interesting background on the evolution of the instructions: http://tomforsyth1000.github.io/papers/LRBNI%20origins%20v4%...

Nyan• 7 years ago

I would almost prefer a more predictable, high-latency decomposition into 4x128 wide uops over what we have now.

AVX512-VL gives the programmer AVX512 functionality at 128/256-bit widths, if it is believed to be more beneficial than a frequency hit.

zone411• 7 years ago

The latest Microsoft Visual C++ has an option to generate AVX-512 code https://docs.microsoft.com/en-us/cpp/build/reference/arch-x6...

Flicki• 7 years ago

Nice work as usual BeeOnRope

Now if only I could actually use avx512 in a desktop, been waiting what feels like 5+ years..

haecceity• 7 years ago

What is this intended to be used for? This [1] article mentions compression, ML, scientific computing. Wouldn't people rather use GPU for those workloads though?

[1] https://devblogs.microsoft.com/cppblog/microsoft-visual-stud...

yvdriess• 7 years ago

Offloading to the GPU has a significant cost that needs to be amortized. DNNs work well because very little is moved over the PCIe bottleneck, and inputs can be buffered. Take modern compression, let's say H265, has a complex control flow combined with highly vectorizable work. I'm unsure where the threshold lies today, but you need a significant amount of work before offloading to and reading back from the GPU becomes interesting on a beefy Xeon.

shaklee34• 7 years ago

This site seems to lock up my phone, but desktop is fine. Anyone else have that issue?

BeeOnRope15• 7 years ago

There are several large SVGs, I wonder if that is the issue.

Can I ask what type of phone you have? Are you willing to help me diagnose the issue?

shaklee34• 7 years ago

I have a really old Nexus 6p. I'm definitely willing to help, but I bet it's just part of having a really old phone.

stolk• 7 years ago

Would disabling “Intel Turbo Boost Technology” be advised to avoid this?

If it never uses turbo, it should not suffer the transitions?

BeeOnRope15• 7 years ago

No, the transitions occur even without turbo. In fact, the chip I tested on has no turbo at all, just 3.2 GHz nominal speed.

Also, disabling turbo would probably be a massive over-reaction, unless you really care out about 99.9th latency or something: the impact of these transitions is small (at worst a few %), while the benefit of turbo is large: 10s of %.

Gathering Intel on Intel AVX-512 Transitions

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