SiFive Announces First RISC-V OoO CPU Core

https://www.anandtech.com/show/15036/sifive-announces-first-riscv-ooo-cpu-core-the-u8series-processor-ip

by vanburen • 7 years ago

137 51 7 years ago

fulafel• 7 years ago

"IP Core" in semi industry terminlogy means a bunch of RTL that is offered for licensing, so this is not yet a working chip.

wolf550e2• 7 years ago

IP cores are sometimes deployed on FPGAs though, so that can be a working chip (depending on definitions).

gnode2• 7 years ago

I think this may be more than a register-level transfer abstraction. The slides make claims about die area and frequency, and show a layout.

SiFive offer IP but also produce SoCs (presumably with TSMC, SMIC, and GlobalFoundries, who are listed as partners).

cfallin• 7 years ago

"IP core" can mean "soft IP", which is just RTL, or "hard IP", which is a full layout (set of mask layers), ready to put on silicon. I haven't read the SiFive announcement closely, but if they're quoting area/frequency/power numbers, it would most likely be the latter.

_chris_• 7 years ago

When you are selling IP like this you would need to do your own physical design due diligence, even if the deliverable is just some Verilog code.

AWildC182• 7 years ago

God I hate that term. It's not your secret sauce intellectual property, it's a fucking library.

Possibly the biggest reason FPGA/ASIC tech has lagged so hard behind CPU/GPGPU in terms of consumer use is because they have managed to use their hardware to completely stifle all open source software (they even go to some lengths to distance themselves from the term "software"). FPGA libraries are almost always encrypted and have to be treated as a true black box when designing. Doing things as mundane as interacting with a PCIe bus or simple signal filtering are all locked away behind ludicrously overpriced "IP" packages that are often vendor specific.

fwip• 7 years ago

Why can't a library be IP?

zozbot234• 7 years ago

Interacting with a PCIe bus does not seem "mundane" to me. Analog electronics is hard, and, just as importantly, process-specific (and the details of any one process are generally kept strictly confidential to the fab, with tightly-binding NDAs). Now, when it comes to pure digital logic I agree, but that's also where open hardware (with meaningful contributions by SiFive themselves) has been most successful.

snvzz2• 7 years ago

Hell, I'm glad Symbiflow[0] exists. Once the toolchain is a little more mature, a library of modules with OSHW licenses is bound to pop up, perhaps even integrated into some sort of IDE.

[0] https://symbiflow.github.io/

jagger27• 7 years ago

A lot of the performance increases of the U8-series come thanks to the increased frequencies capabilities which are 1.4x higher this generation, with the core scaling up to 2.6GHz on 7nm.

Pretty cool that these chips are approaching performance parity so quickly.

baybal2• 7 years ago

SiFive’s design goals for the U8-Series are quite straightforward: Compared to an Arm Cortex-A72, the U8-Series aims to be comparable in performance, while offering 1.5x better power efficiency at the same time as using half the area.

This is very a big statement. It's hard for me to think of how they do that, when 8th gen ARM cores are said to be blowing just anything else on size/performance ratio.

Where does SiFive get such an expertise in size optimisation?

wmf• 7 years ago

I wonder if that's comparing the non-vector U84 against the A72 with Neon.

brucehoult3• 7 years ago

It will be, yes, and the U87 with a vector unit will obviously be a bit bigger. There are many applications where a vector unit is unnecessary silicon that adds nothing but cost and power consumption.

audunw• 7 years ago

The RISC-V ISA was made with some hindsight of what choices makes it easy to optimize for OoO superscalar CPUs. If I remember correctly, that's one of the reasons everyone jumped ship from OpenRISC to RISC-V (the big mistake in OpenRISC being branch delay slots I believe)

It might also help starting from scratch.

I'm also not convinced it's entirely an apples-to-apples comparison. ARM might support more complex instructions that their core don't, and the ARM core might have features like TrustZone.

cesarb• 7 years ago

The RISC-V ISA was made with some hindsight of what choices makes it easy to optimize for OoO superscalar CPUs.

ARM's 64-bit architecture (AArch64) was also made with similar hindsight, so that's probably not the whole reason.

thesz• 7 years ago

OpenRISC also has divide overflow exception and integer overflow exceptions. Both are generally avoidably with the "exception with code" instruction, some little condition checking and some small compiler work.

MIPS, for instance, does not have divide overflow exception. It uses compare, conditional branching and "exception with exception code" instruction.

Most of the time (int32_t/int32_t) division is safe, because divisor is checked for zero in the code logic somewhere else and guaranteed to be non-zero. Sometimes (int64_t/int32_t) it is not safe (higher word is divident can be bigger than divisor) and checking code must be executed in run time. And execution overhead is so little that it is quite good design choice.

You don't have hardware that drains energy constantly for slight slowdown for code that is rare.

As far I can remember, RISC-V does not have divide overflow exception.

As a rule of thumb: if you can put something into software, please do (overflow checks, code scheduling instead of delay slots). Hardware is for things where software can't help (branch prefetch, out of order, etc).

kick• 7 years ago

SiFive was founded by most of the initial RISC-V designers, and is easily one of the companies with the most raw talent in the field right now.

monocasa7• 7 years ago

Yeah, Apple('s acquisitions) are probably the closest in terms of raw talent, and their cores aren't being compared here for a lot of reasons.

rrss• 7 years ago

7nm instead of 16nm probably helps a lot.

brucehoult3• 7 years ago

The A72 supports at least three completely different instruction sets (A64, A32, T32), which has a cost. You could make a much sleeker A64-only CPU core as Apple, Cavium, and Fujitsu do, though it's still not going to be as sleek as RISC-V.

dmitrygr• 7 years ago

it's still not going to be as sleek as RISC-V

Why? A64 is a completely new design, and unlike RISC-V, by people who've been doing it a while professionally and successfully

jeanmichelx• 7 years ago

I doubt their numbers are correct. They've fudged them in the past, giving area numbers for the smallest configuration, but performance number for a ridiculously large chip.

bcheung2• 7 years ago

I wasn't sure what OoO stood for and since they never mentioned it in the article I had to look it up. For anyone else who is asking the same question.

OoO = out of order execution

SlowRobotAhead• 7 years ago

I’m right there with you!

I’ve been doing embedded hardware and CE work for 15 years non-stop, and had no idea what OoO meant.

Kept thinking “on a”. As in SoC or PoC.

BookPage• 7 years ago

It’s actually mentioned in a header after the third paragraph in the article...

bcheung2• 7 years ago

Yeah, I saw that later on when I continued reading. I did a Find on the page and was looking for "ooo" and didn't find anything like "order of order (ooo)" because it's customary to define it when it is first used.

yhvh3• 7 years ago

Is there a risc-v chip on the market which includes Bluetooth?

arcticbull• 7 years ago

Usually Bluetooth modules are add-on peripherals, unless I'm mistaken.

aneutron• 7 years ago

Exactly what I was thinking when I read the parent at first, but I'm assuming the parent is asking about all-in-on SoC chips.

Taniwha• 7 years ago

yes but expressif's big plus is low-cost wifi/bluetooth integrated with a CPU/flash/ram

childintime• 7 years ago

Espressif is planning a RISCV based ESP32 upgrade, it'll probably will have Bluetooth. No schedule yet.

Shtirlic• 7 years ago

SiFive HiFive1 Rev B with esp32(WiFi/BT (off-chip))

yhvh3• 7 years ago

Yeah I know about this, I need it all in one package.

mattnewport• 7 years ago

A Raspberry Pi type SBC based on this would be neat, is that something we can expect to see any time soon in light of this announcement or is that not an application this is really aimed at?

snvzz2• 7 years ago

This is most likely to come from lowrisc[0] instead.

[0] https://www.lowrisc.org/

brucehoult3• 7 years ago

That would be neat, and would come out somewhere similar to a Pi 4 (which are pretty awesome).

Note that the Pi 4 has ARM processor cores, but ARM doesn't make either the processor chip or the board. Broadcom design and make the BCM2711 SoC, and the Raspberry Pi Foundation designed and manufactures the board.

No doubt SiFive would be very happy to work with someone who wanted to make retail SoCs and/or SBCs using the U84, but as with ARM it's not really their business model to do that themselves.

SiFive has made several low-volume chips and boards for potential core IP customers to use for evaluation and development e.g. the $999 HiFive Unleashed. ARM similarly offers a $10000 dev board for the A72.

monocasa7• 7 years ago

Have we gotten confirmation yet on whether this is a BOOM core or not? It certainly feels like it is

SiFive Announces First RISC-V OoO CPU Core

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