The Surprising Subtleties of Zeroing a Register (2013)

https://randomascii.wordpress.com/2012/12/29/the-surprising-subtleties-of-zeroing-a-register/

by ingve • 7 years ago

102 22 7 years ago

randomascii.wordpress.com

RyJones• 7 years ago

(2013)

The article was written in 2012, but was last updated in 2013, so dealer's choice?

plucas• 7 years ago

Written December 29th and updated 9 days later. :)

rayiner2• 7 years ago

As to the 4 instruction limit, see: https://www.realworldtech.com/sandy-bridge/5.

The register rename stage, which does the zeroing, can handle four instructions per cycle. It’s not immediately obvious from the picture, but after instructions are fetched from the uop cache, they are sent to a 28-entry decoder queue, which can act as a small loop buffer. From there, four uops per cycle are sent to the allocate/rename stage (which is part of the ROB block in the first picture).

jabl• 7 years ago

It's said in the article, under the "Update: January 7, 2013" heading.

saagarjha• 7 years ago

CPU designers could create a design where an xor instruction was faster than a sub instruction. However that would mean that sub would take at least two clock cycles, since instruction lengths are integer cycle counts. Unless this modification let them at least double the clock speed it would be a net loss. It’s better to make xor take just as long as sub. You can’t make an xor instruction take, say, 0.6 cycles. But feel free to try.

Earlier, the article says that the process can perform four instructions per cycle. Just to confirm, this isn't normally referred to as taking "0.25 cycles per instruction", right?

wongarsu• 7 years ago

There is some parallelism within in each CPU core so it can do four additions each cycle. But those don't happen after each other, they happen simultaniously. From an eagle eye's view it can look like 0.25 cycles per instruction, so on a higher abstraction level that's a valid view on it. But in reality they start and end at the same time each takes one cycle.

rayiner2• 7 years ago

The Intel manuals sometimes use that as a shorthand, but no, it’s usually not. The difference is between throughout and latency. You can process four independent instructions per cycle in parallel (if none depend on the results of the others), but the results of a given instruction will take at least one cycle to be available for the next instruction that uses it as an input. (It takes 9 months to make a baby even though you can make more than one at a time.)

Sean1708• 7 years ago

You can process four independent instructions per cycle in parallel

is this down to pipelining, or is that separate?

jcranmer2• 7 years ago

The time instructions take are usually boiled down to two metrics: reciprocal throughput (you can issue 1 instruction of this type every N cycles), and latency (an instruction can use the result of this instruction N cycles after it executes). Latency is necessarily an integer number of cycles, but reciprocal throughput can be less than 1 if there are multiple execution ports in a superscalar machine.

For example, the latency of a multiply instruction is usually about 3-4 cycles. But the reciprocal throughput is generally 1 (or 0.5 if you have two multiply units)--the execution unit is pipelined to allow a new input every cycle.

richardhod• 7 years ago

This is highly appreciated: the kind of advanced, specific knowledge that your average hacker might not know, but should improve their/our thought processes, efficiency, reliability security and general understanding of programming. This is one of the primary reasons HN is so valuable, and I do wish there were some good repository of the best of these kinds of article to browse, apart from searching HN, which like anything can be noisy.

jakeinspace• 7 years ago

I recently had an interview at one of the big chip designers, and towards the end they gave a few basic computer architecture and assembly brainteaser questions. One of them was whether I was aware of a smaller instruction for zeroing a register, and I did manage to guess xor after a little thought. It's a trivial idea, but very satisfying to realize for the first time.

brucedawson4• 7 years ago

Author here - I just want to drop in to reiterate how awesome register renaming is. It's a bit weird to try and understand, but it is crucial to how these out-of-order processors run, and it is the trick which lets the register zeroing run so efficiently.

An x86-64 CPU has sixteen integer registers, but 100-200 physical integer registers. Every time an instruction writes to, say, RAX the renamer chooses an available physical register and does the write to it, recording the fact that RAX is now physical-register #137. This allows the breaking of dependency chains, thus allowing execution parallelism.

In the case of the zeroing instructions the register renamer says "RAX now maps to physical-register #0" where that is a register reserved for the purpose of being zero. No execution is needed. It's beautiful.

For more details read up on out-of-order execution and register renaming.

theoh2• 7 years ago

This is a good place to start: https://en.wikipedia.org/wiki/Tomasulo_algorithm.

Butler Lampson mentions register renaming as one of a dozen paradigmatic neat techniques in this 2015 presentation:

http://bwlampson.site/Slides/Hints%20and%20principles%20(HLF... Edit: corrected link

It's easy for software people not to ever encounter it!

brucedawson4• 7 years ago

It's easy for software people not to ever encounter it!

Yep, because it does its magic without any intervention required.

One concrete example that I like is this:

mov rax,[rsi+0] mov [rdi+0],rax mov rax,[rsi+8] mov [rdi+8],rax

This moves sixteen bytes of memory, all of it going through rax. Without register renaming the third instruction can't run until the second instruction completes, because they're both using rax. With register renaming the third instruction uses a different physical register for rax, and the out-of-order engine can do the loads in parallel and the stores in parallel.

Before anybody freaks out - register renaming doesn't change the semantics of your program. It just makes your program run faster. It just means that you can write code like the above - there's no need to rearrange the instructions and use multiple temporary registers, because the CPU will do it for you, and will dirty fewer architectural registers.

The Surprising Subtleties of Zeroing a Register (2013)

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