swetland

I create value the same way I always have.

Meanwhile people are creating garbage with "ai" tools. I wish them the best of luck with their shit.

Fuck off. No, I'm not using it. No, I'm not enjoying it.

The only thing performative around here is all you assholes evangelizing this worthless shit.

It's useful indicator in these days of useless slop coded shit. Few things are a bigger waste of my time than reading about someone's proudly "ai"-generated pile of garbage.

Actually it's quite useful information. As soon as I see another useless "ai coded" project I immediately stop reading/caring about it. Fuck your slop code. Nobody wants that shit.

There is no way this utter pile of slop was written by a human.

Don't suppose there's actually documentation for the CPU anywhere? (I mean more than a tiny "datasheet" with a very high level overview and/or a pile of random Linux/uboot patches)

Lots of nice improvements here. The RISC-V RV32I option is nice -- so many RV32 MCUs have absurdly tiny amounts of SRAM and very limited peripherals. The Cortex M33s are a biiig upgrade from the M0+s in the RP2040. Real atomic operations. An FPU. I'm exited.

They actually let you choose one Cortex-M33 and one RISC-V RV32 as an option (probably not going to be a very common use case) and support atomic instructions from both cores.

That's the expected clock rate for the TT07 run... but Tiny Tapeout designs only have 8 in, 8 out, and 8 bidirectional IOs (plus a reset and clock input) available, so they're using a multiplexing strategy where the Z80 clock runs at 1/4 of the base clock rate and alternates between control signals, A0-A7, control signals, and A8-A15 on the OUT pins:

https://github.com/rejunity/z80-open-silicon/blob/68438f0019...

So you'd get an effective 12.5MHz Z80 clock and need a bit of external logic to demultiplex the full IO interface. Still not too shabby!

The goal (per the project README) appears to be to prototype with TT07 and then look into taping out standalone with ChipIgnite in QFN44 and DIP40 packages (which would be able to have the full traditional Z80 bus interface and run at the full clock rate).

Yeah, the whole "what could we do with the original CPU and PPU of the NES given much more RAM and game data storage" experiment is pretty neat -- and based on what they've shown so far the results are quite impressive.

I had moved on from Android by 2013, so I definitely don't have much insight into what it's become over the past decade. In the earlier years it was very much about working hard to build the platform, products, and ecosystem. The team was pretty small and generally isolated from the rest of the company, which was both good (we got to focus on doing our thing and not get distracted) and bad (integrating with Google properties, services, etc was often rather painful).

Part of the reason I left the team was Clockwork (before it became Wear) turning into "just cram Android on to a watch", which was very much not an approach I was excited about and things getting more political and "too big to fail", combined with burnout and needing a change of scenery.

The whole "throw everything in the trash and start over" thing is massively overstated. The iPhone announcement absolutely impacted things, not entirely all bad -- there was interest from OEMs before that, but it went through the roof after -- and it did mean we moved from the plan to ship a blackberry-style device first followed by a touchscreen device to skipping right to touch for initial launch, recognizing that the landscape had absolutely changed.

Initial work on the touchscreen based hardware started back in June 2006 (I remember meeting with HTC during a monsoon to kick off the project that became Dream/G1) and OS work to support larger displays, touch input, etc was underway before iPhone was announced.

Blackberry was not really the concern early on... Windows Mobile was. Folks (correctly as it turned out) believed mobile was going to be the next big platform area and there was concern (from Google, but also from OEMs, cellular carriers, etc) that Microsoft might end up entrenching themselves the way they did in PCs through the 90s, possibly including a more successful attempt to control the browser/web experience.

Yeah, I take exception to the painting of Android as inherently "unhealthy" and not "solving real problems for users." Also with lumping it in with the unmitigated disaster that was the Social/G+ effort. I attribute much of Android's success to Larry & Eric being very supportive, shielding the team from constant interference from the rest of the company, and letting us get shit done and ship.

I came aboard during the Android acquisition, some months before he started at Google, so of course I may be a bit biased here. I was pretty skeptical about landing at Google and didn't think I'd be there for more than a couple years, but spent 14 years there in the end.

Android had plenty of issues, but shipping consumer electronics successfully really does not happen without dealing with external partners and schedules that you can't fully control.

No idea what the laundry bins thing is about -- never saw that.

Oh I don't even mean the FPGA side (of course that'd be nice), just the SoC's CPU complex and its peripherals! The only "documentation" I've found is a high level block diagram.

Not finding any documentation for this SoC on either the beagleboard or microchip websites. I'm still waiting for a RISC-V SoC that actually has reasonable documentation instead of a pile of random linux kernel and (maybe) bootloader patches. A list of base addresses for peripherals and a block diagram does not count.

The intent behind the vDSO style interface for syscalls in Fuchsia was primarily to avoid baking specific syscall mechanisms into the ABI, hopefully to allow future changes to the mechanism without breaking binary compatibility -- which was defined as ELF linkage against libzircon.so.

Most of that was when the team was pretty tiny. It was fun starting from when the kernel was just beginning to run userspace code. I'm still very happy with how the syscalls turned out. If I did it again, I'd stick with a (small) monolithic kernel though -- makes a lot of things simpler.

SiFive has pretty good documentation for their cores and chips -- they are more PC/Server class (some lowspeed peripherals plus PCIE and Ethernet) than SoC style. The databook does not have register level docs for PCIE and Ethernet but both look like off-the-shelf IP (hopefully documented somewhere -- I haven't investigated) but otherwise seems pretty thorough.

https://www.sifive.com/documentation

In addition to a documented RV64 SoC, it'd be cool to see some RV32 MCUs that are a little beefier -- more competitive with the mid-range Cortex M4 and M7 stuff (more peripherals, more SRAM, etc) -- instead of the existing stuff that looks similar to very tiny M0/M3 devices.

Okay, so is there actual documentation for the SoC used on this critter? I mean a full Databook / Technical Reference Manual, not maybe 30 pages of overview, maybe a list of register base addresses (if you're lucky), and a pile of Linux kernel patches (upstream if you're lucky, but still of less value to someone wanting to actually write code for / port something to the SoC) or an "SDK" containing a bunch of low quality vendor code for the peripherals.

I'd love to see a RISC-V SoC (not just a dinky little MCU) that has real / complete documentation. So far I have yet to find any for any of the various RISC-V based SBCs that have shipped.

The place where it breaks down is if you want to build a keyboard that doesn't use a typical collection of contours and widths of keys or a subset thereof. I haven't found a shop that'll do a "nonstandard" collection of keys as a package and the prices for one-off custom keycaps are not economical for a set of 50 or 70 or whathaveyou.

It's replicating the ZX81 keyboard, including all the quirks except for the horrific membrane keys.

https://upload.wikimedia.org/wikipedia/commons/8/8a/Sinclair...

The ZX80 and ZX81, like a number of 80s personal computers featured a set of graphical characters in addition to standard alphanumeric and punctuation and provided a way to enter then directly from the keyboard. On the Sinclair machines you'd use SHIFT + GRAPH to enter "graphics mode."

https://upload.wikimedia.org/wikipedia/commons/e/e9/Commodor...

https://upload.wikimedia.org/wikipedia/commons/9/9a/Atari-13...

I've had a lot of fun with this project, but want to be clear that the actual "replicate the ZX81 using discrete 74xx logic (like the ZX80) instead of the ULA chip" PCB design is the work of Mahjongg2 who has shared their work here:

https://github.com/mahjongg2/ZX81plus38

https://forums.raspberrypi.com/viewtopic.php?t=254492

https://revspace.nl/ZX81plus38_simple_to_build_ZX-81_clone

Somewhat amusingly, the keycaps were the most expensive component ($60 plus shipping), second most expensive being the keyswitches. I really wanted something that captured all the information presented by the original keyboard and also fit on keycaps and am pretty happy with the result.

The CPU itself (Core Complex, including cache, irq controller, etc) is documented by SiFive:

https://www.sifive.com/cores/u74-mc

Unfortunately there appears to be no detailed documentation at all (unless you count a pile of Linux and bootloader patches, which I don't) for the peripherals, etc, outside of the core complex on the SoC:

https://doc-en.rvspace.org/Doc_Center/jh7110.html

It's definitely nicer to have source than a bunch of opaque binaries. (Is there source for the full boot path? Sounds like they have patches for OpenSBI and u-boot -- didn't see if there was source or docs for the on-die boot rom.)

I just find the "all you need is Linux patches" approach annoying. There are BSD variants and little experimental and homebrew OSes out there that would be fun to run on a capable RISC-V SBC and even if you are using Linux it's still nice to have some documentation to refer to beyond whatever the silicon vendor implemented in various driver patches.

Still no sign of an actual Technical Reference Manual or any other detailed documentation on the SoC (registers, peripherals, etc). A big pile of Linux patches, while better than nothing, is a poor substitute for actual documentation.

SiFive does provide docs for the core complex (processors, cache, irq controller, etc), but that doesn't cover any SoC-specific peripherals.

This repo archives a bunch of ncsa httpd releases: https://github.com/TooDumbForAName/ncsa-httpd

cgi_src/jj.c exists in 1.1, but not 0.5 (and no versions between those two are in the archive)

0.5 - 6 sep 1993 - http://1997.webhistory.org/www.lists/www-talk.1993q3/0828.ht...

1.0 - 13 dec 1993 - http://1997.webhistory.org/www.lists/www-talk.1993q4/0811.ht...

1.1 - 24 jan 1994 - http://1997.webhistory.org/www.lists/www-talk.1994q1/0282.ht...

I suspect it was added by 1.0 as that's when "the htbin stuff is no longer distributed, CGI/1.0 versions of your old favorites are included instead", but definitely exists in the 1.1 snapshot on github.

It was modified or removed at some point later on, after complaints from Jimmy Johns about abuse.

The "ISA" mentioned above is the "Industry Standard Architecture", the 8/16bit bus used by PCs and PC clones back in the day, not "Instruction Set Architecture (x86, ARM, RISC-V, etc): https://en.wikipedia.org/wiki/Industry_Standard_Architecture

Using half of zero-page for IO (and then dedicating 1/4 of that to a string printing interface) is a somewhat odd design choice. Most nontrivial 6502 software leans heavily on zero page (since there are very few registers and shorter/faster instructions for zero-page memory access).

Simulating something that looks like a serial port (transmit/receive/status registers) would seem more natural, peripheral-wise.