HN user
The key question is which workloads will actually benefit from many low single-thread performance cores. While there are some where such a node coupled with a GPU compute cluster will probably be the useful but it seems like a vast majority of server deployments just want good single-thread perf with 2 or more hardware threads.
A much bigger problem "holding up Moore's Law Progression" is the failure of Dennard scaling and the fact that voltage scaling is hitting the threshold voltage limit (where sub-threshold leakage current increases significantly) as we move to smaller technology nodes. This means we can build bigger chips but we don't necessarily have the power budget to power up all parts of it at the same time (these could be cores, pipeline structures, etc). The architecture community has written a lot on this "Dark Silicon" problem if anyone wants to read further.
As a CPU architect, I can confirm that all those except possibly 2) will not yield significant benefits. Prefetching hints will only be useful when the particular code fragment is highly memory-bound because most wide superscalar microarchitectures will easily hide L1/L2 miss latencies.