TanjB

No, this is panels from which interposers will be made. Which are now larger than chips and rectangular, so wasted edges from a 300mm wafer are high. The proposed size is much larger than chip-grade ingots.

They don't need perfect silicon. It can be grown on a continuous ribbon which is sliced into panel sizes like they do for solar cells. If they need a perfect surface they can deposit some pure Si to finish it. Maybe we will eventually see that replace ingots for chip grade.

MIPS had load const to high or low half. More that 40 years ago Transputer had shift-and-load 8 bit constants. Lots of ancient precedents for rare big constants.

Interesting idea. Effectively moving the extra decode stage in front of the Icache, making the Icache a bit like a CISC trace/microOp cache. On a 512b line you would add 32 bits to mark the instruction boundaries. At which point you start to wonder if there is anything else worth adding that simplifies the later decode chain. And if the roughly 5% adder to Icache size (figuring less than 1/16th since a lot of shared overhead) is worth it.

When Moore wrote in 1965, commercial use of MOS was 10 years in the future and Dennard scaling would not become widely understood and stirring interest in CMOS until 15 years in the future. So, he was actually observing an era much like now, with multiple chiplets inside the can and all sorts of random improvements that had an emergent trend. The Dennard era, which gave Moore its main impulse, was about 20 years long. Maybe 25 years if you include controlling tunnel leakage by introducing Hf-based dielectrics, and FinFETs since they sort of crinkle the surface of the chip to give you double the area, and otherwise obey classic Dennard laws of constant power per unit area.

But even during the Dennard era there were a bunch of big random innovations needed to keep things going. CMP allowing the number of metal routing layers to balloon, keeping distances under control. Damascene metals allowing much finer metals carrying heavier currents. Strained channels for higher frequency and better balance between P and N. Work-function-biased fully depleted transistors to avoid the stochastic problems with doping small channels. Etc.

So what really happened is not that Moore ended. We still have a wealth of random improvements (where "wealth" is the driving force) which contribute to an emergent Moore improvement. But the large change is Dennard ended, which gave us scaling at constant power. Although some of the random improvements do improve energy efficiency per unit of computation, they are not overall holding the line on power per cm2. At the end of the classic Dennard we were around 25W /cm2 but now we commonly have 50W in server chips, and there are schemes in the works to use liquid cooling up to hundreds of W / cm2.

Well, ok. But does that kill Moore? Not if it keeps getting cheaper per unit function. And by that I do not mean per transistor. But as long at that SOC in your phone keeps running faster radio, drawing better graphics, understanding your voice, generating 3D audio, etc., and is affordable by hundreds of millions of consumers, Moore remains undead.

DRAM is not greatly affected by radiation, because the capacitors are large structures relative to radiation events. SRAM is affected, which is why SRAM arrays should always use SECDED ECC.

The dominant cause of DRAM failures is bit flips from variable retention time (VRT), where the cell fails to hold charge long enough to meet refresh timing. These are believed to be caused by stray charge trapped in gate dielectric, a bit like an accidental NAND, and they can persist for days to months. This is why the latest generation (LPDDR4x, LP/DDR5) have single bit correction built into the DRAM chip. Along with permanent single cell failures due to aging this probably fixes more than 95% of DRAM faults.

The DRAM vendors sure could do a lot better on publishing error statistics. They are probably the least transparent critical technology used in everything, but no regulation requires them to explain and they generally refuse statistics on faults even to major customers (which is why folks like AMD run large experiments at supercomputer sites to investigate, and most clouds gather their own data).

That said, DRAM chips are pretty good. The DDR4 generation probably had better than a 1000 FIT rate per 2GB chip, so in a laptop with 16GB that would have been less than 10 error per million hours, or under 1 per 50 laptops used for a year.

For many of us the vast majority of data is in media files. I personally notice broken photos and videos every now and then. I would love to have a laptop with a competent ECC level, but they do not exist. Even desktop servers often come without. It is unclear how much better the LP/DDR5 generation will be since the on-die ECC still does not fix higher order faults in word lines and other shared structures, which may sum to as much as 10% of aging faults. All simply educated guesses, since the industry will not publish.

Those cell sizes are theoretical anyway. They do exist, but on sample chips optimized for SRAM. If you design a chip and select an IP macro for SRAM the density you actually get may be 3x or larger per bit. This is due to compromises on the process the rest of the chip goes through, the need for row and column periphery, ECC, and ports. One advantage the Z-cache has at AMD is the cache chip appears to be optimized for SRAM. It has 2x the capacity of the cache on the CPU chip even though it directly matches the overall cache outline on the base.

The main problem with scaling is that SRAM found an optimal layout in FinFET with no significant wiring issues. While scaling from 7nm on down none of the tricks that benefit logic density - fewer lines, reduced gaps, contacts over active gate - SRAM does not need them. It was already optimal. The only thing it benefits from is honestly finer features, which is happening only slowly.

The next major jump expected is CFET where going vertical is matched by a new optimal pattern that takes advantage if the N and P being above each other. That is generally expected for N2/20A processes.

Nice idea, but I honestly don't think it has much value for study. It was a solution to a problem which is no longer important, and what impressed David (and was fun for me) was implementing it under constraints (8086) that are no longer relevant. I would vote for some of the other stuff mentioned by others, like TeX as an example of mastery of both the application requirements with beautiful algorithms and inspirational documentation, PostgreSQL as a thriving large system with brilliant modularization that has enabled research, or LLVM as a pinnacle of code generation which has enabled a golden era of language and hardware design over the last 20 years.

TeX was beautiful. Both the algorithms (it was a masterwork on typesetting, still a good reference for anyone doing text layout) and the book.

Hi David, thanks for the kind words. I still have the source for that I think, it was written around 1984 originally for a project of my own, then sold to Logitech, Zorland, and Borland (before I went to work for Borland). The Borland one was probably tweaked a bit - like you my memory does not include details.

There were 7 registers to play with. AX, BX, CX, DX, SI, DI, and occasionally BP. MS-DOS had no rules about frame pointer although later Borland would prefer it was kept to a standard use so that exceptions can be handled.

It would have run faster in 32 bit. Many fewer cross products for multiply and faster convergence for division and sqrt, plus just fewer registers needed. But updating the entry and exit code may have been the largest win. By the mid 1990s the FPU was moving onto the CPU chips even at the low end so the main goal would have been stability and backwards compatibility.

I wrote assembly code for many machines before and after that. In the early days such careful juggling of registers was routine. I generally wrote my algorithms in Pascal (later in Modula or Ada and by Borland days, in C++) and then hand compiled down to assembly. That separation of algorithm and coding stopped it getting too tangled.

Thanks for the shout out! These days I write System Verilog (algorithms modelled with C++) for hardware projects, and Julia for the pure software.

Memory fail. No ECC, uses DDR4 instead of LPDDR4x (which has a 1-bit ECC and superior bandwidth) which the Tiger Lake CPUs would support.

Apple is probably paying closer to $20k per wafer, including test and packaging. There have been leaks on pricing in the industry, leading edge process is expensive. Even at 50M chips. TSMC is in a position to command a price that pays to build the next gen fab, and there are other customers.

Masks are also a significant expense. N5 is an EUV intensive process with $10..20M per set. They probably run through a new mask set every 50,000 wafers or so, and likely need 2 mask sets to get beyond 10,000 (two days) so they can swap them out for inspection and cleaning. So their mask costs for the 100,000 wafers they need are somewhere above $50M.

It is interesting to compare with a project like Graviton2 on N7, which is more like $12k per wafer including test and packaging and likely 120 chips yielded at 4cm2 each. They probably need 2M chips per generation, and as their design is not nearly as aggressive as the A14, with far fewer different functional blocks and mostly off the shelf IP, they may have done it with as little as $200M of R&D. So they can get a G2 for as low as $200, maybe as much as $300. That makes each core $5 or less. About a third the price of the DRAM they need per core.

Ironic. CMP was developed and perfected at IBM, who used it to make complex low volume products.

Excellent insight. CMP and damascene metal (guess who!) really kicked CMOS into top gear.

Some of the issues in the original paper are real (except the hologram where they have transformed marketing hype for stereo images into a real expectation of transmitting holograms). Pretty much all of them are capable of being implemented by tunneling through specialized transports, without needing to replace IPv6. After all, that is the "inter" in internets - you are already free to have specialized subnets. Cray implements low latency transport for IP in their supercomputers. You can use a VPN to anonymize your traffic, including transforming the addressing. And so on. If you step through the original presentation, everything is something you are free to implement and make available via IP ports as a subnet.